JPS5961040A - Integrated circuit - Google Patents

Abstract

PURPOSE:To realize the test of D/A converter with a test signal having less number of bits and reduce a size of integrated circuit by applying a test signal for DA converter through arithmetic operation circuits. CONSTITUTION:A data processing circuit 11 is formed with a pattern generator 21 and an operation circuit 22 and an output of such circuit 11 is applied to a waveform memory 13 and a selection circuit 14. The selection circuit selects a counting signal B sent from the operation circuit 22 and a waveform signal C sent from the waveform memory 13 and applies them to a DA converter 16. In the ordinary operation, an input data A is input to the terminal 12 and a corresponding waveform signal C is supplied to the DA converter 16 from the waveform memory 13. In the case of executing the test of DA converter 16, the test signal E is input to the terminal 17 and the corresponding count signal B is supplied to the DA converter 16.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to an integrated circuit in which a digital part, an analog part + 7) coexist, and is particularly useful for conducting a trial theory of a built-in digital-to-analog (DA) conversion circuit. Regarding circuits and configurations.

[Technical background of the invention and its problems]

The electrical characteristics of the DAf-L'A circuit, which is integrated into the circuit, influence the characteristics of the integrated circuit itself, and understanding these characteristics is an important problem.

As a way to determine the characteristics of a DAA conversion circuit, you can roughly determine the time characteristics by comparing the data information input to the integrated circuit and the output signal at that time, but it is impossible to understand all the characteristics. be.

Conventionally, the circuit configuration shown in the first example has been considered as a method for testing the chemical characteristics of a DA liquid inlet circuit built into an integrated circuit.

A data processing circuit (1) processes data information a inputted to a terminal (2) and outputs an M-bit count signal.

Waveform R, OM (31 uses the above counter No. 8 as an address input to generate a digital waveform/I information signal C consisting of N pits. The selection circuit (4) receives an external command signal d input from the terminal (5). When testing the Yoshi DA conversion circuit (6):
outputs the N-bit external input signal e that enters from the terminal (power).In the normal state, the digital waveform is selected from the A conversion circuit (6). This DA converter circuit (6) generates an analog signal f and outputs a terminal (
8).

In this way, when testing the I) A f circuit (6), all the abnormalities can be known by inputting arbitrary data as an external input signal to the terminal (7). However, having the l) terminal (power) of the external input signal from N bits (e.g. 8 bits) in the integrated circuit means using a package for the discrete circuit that is larger than necessary, making it compact. In addition, routing the N-bit external input signal e to the chinov by '3' causes the circuit design to become more complex.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an integrated circuit that can test a DA conversion circuit by simply inputting a test signal with a small number of bits.

[Summary of the invention]

The present invention has a configuration in which a test signal for testing the DA conversion circuit can be input into the arithmetic section of the data processing circuit, and furthermore, the selection circuit J@ is external! Ij! The digital waveform signal output from the waveform generation memory or the count signal output from the data processing circuit is selectively input to the DA conversion circuit under the control of the I output signal.

〔Effect of the invention〕

According to the present invention, a test signal inputted from the outside is inputted to the arithmetic unit of the data processing circuit, subjected to 6-beta calculation, and then inputted to the DA conversion circuit, so there is an advantage that a test signal with a small number of bits is required. .

[Embodiments of the invention]

An integrated circuit Oθ) according to an embodiment of the present invention is shown in Figure 2.

The data processing circuit 0υ takes in the data information A input from the terminal (+21) and inputs it to the input data fr 'fft.
3 (
21), the putter 7 signal A1 and the outside ti of the 3 pits, for example.
The lt test signal E is added and counted, and the arithmetic unit 0 generates the a11 signal B. Waveform ROM (+3) uses count signal B as address input and outputs digital waveform signal C.
occurs.

The selection circuit a4) receives the external input signal D input to the terminal Q
; Therefore, in the normal mode, select the digital waveform signal C, and in the test mode, select the count signal B, and select D.
A; 4: Mata rotation l〆δtliij &C output. D
The A f converting circuit U []) outputs a waveform signal F converted to an analog signal.

By turning on the circuit 410, the pattern signal "-'jA1" is stopped in the test mode, and the test No. 18/
From Riko, who performs H using only E as input, test (r
- By setting the T number E, it is possible to generate Riu (n number I3) of various periods.
ii control signal, select D A change 1i thigh circuit (16
), the rJAfi conversion circuit α0
It is possible to know the physical characteristics of Also, the count signal J
3 By observing is-analog data, it is possible to understand the ir1 production status of the data processing circuit (value of lυ) ψ part of ez, and it can be applied as a simple check when manufacturing integrated circuits. be. Similarly, by stopping the input of one test signal and inputting -data information A, a simple check of the pattern generation section (21) is also possible.

In the above embodiment, the waveform ROλ4 is used, but generally any memory that generates a waveform corresponding to j may be used.

[Brief explanation of drawings]

2n 1 diagram shows an integrated circuit of ilE US; (iJ showing 4 turns)
1. 2. 4 is a diagram showing the configuration of the present invention - an actual Kusunoki row. lO: integrated circuit 11: data processing circuit 13
・・Wave form OM 14・Sensawa times・Raku 16・・D
A, J: fi: circuit 21... putter, 7 generation part 22... performance part 1

Claims (1)

[Claims] It consists of a pattern generation section that generates butter No. 713 corresponding to input data information, and a calculation section that performs a predetermined calculation using this pattern signal and a test signal input from the outside during testing as input and outputs a count (i. A data processing section, a waveform generation memory that receives the above-mentioned total &i 13 as input and outputs a digital waveform signal according to this signal, and selects and outputs the digital waveform signal output from this memory or the above-mentioned count signal by means of an external control No. 18. What is claimed is: 1. An integrated circuit comprising: a selection circuit for converting an output signal of the selection circuit into an analog signal;