JPH01153985A - Pattern generating device - Google Patents

Abstract

PURPOSE:To inspect all patterns by providing a 1st storage means for storing a previous pattern temporarily, a 2nd storage means for storing the expected value of an arithmetic result, and a 3rd storage means for storing a noncoincidence signal outputted by a comparing means. CONSTITUTION:A pattern '0' which is generated 1 is inputted to a register (RE) 2 with a 1st clock. The output value '0' of the RE 2 is inputted to a RE 3 with a 2nd clock and the RE 2 inputs a next pattern '1'. Then, an arithmetical logical operation circuit 4 subtracts the output value of the RE 3 from that of the RE 2 and outputs the result '1' to a comparing circuit 6. This circuit 6 decides that the output value '1' coincides with the output '1' of a register 5. Therefore, a FF 7 is in a '0' state. Further, the RE 3 inputs the output '2' of the RE 2 with a 3rd clock and the RE 2 takes in a pattern '0'. Consequently, the circuit 4 subtracts the output value of the RE 3 from that of the RE 2 and outputs the result '-1' to the circuit 6. This output value '-1' is compared with the output value '1' of a RE 5 to perform a decision 6 on their noncoincidence.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor testing device, and more particularly to a pattern generator suitable for testing patterns generated by a pattern generator of a memory tester.

[Conventional technology]

In the conventional method, as described in Japanese Unexamined Patent Publication No. 54-150087, a counter counts υ every time the pattern generated every cycle by a pattern generator changes, and the amount of change of 0.1 in the pattern is calculated. ), the occurrence pattern was determined to be normal or abnormal based on whether the result matched a pre-prepared expected value.

[Problem that the invention seeks to solve]

The above-mentioned prior art uses 0.0% of the pattern from the pattern generator.
It only counts the amount of change of 1, and the change in pattern for each cycle is +! It had not been inspected.

A specific example of this will be explained using FIGS. 3 and 4.

Figure 3 is an example of a timing chart when an incorrect pattern is generated, and the pattern in the third cycle is @2”
It is assumed that the difference is from 10″ to 10″.

FIG. 4 shows the generation pattern of the third pattern generator 1 in 1-bit units. In the incorrect 9th pattern in FIG. 3, the pulse does not go to H in the third cycle of the second bit.
The signal became H after a delay in the fourth cycle. As shown in FIG. 4, when the pattern change is delayed by one cycle, the conventional technology only counts the amount of change of 11, and if the change occurs at 6D and the third takele, then 4? In either case, the amount of change is the same, so the result is determined to be normal.

As in this example, with the prior art, an error in the amount of change in [lLl] can be found, but an error in the change time of [Ll] cannot be discovered.

Furthermore, in the prior art, pattern testing only requires that the overall result match an expected value, and no consideration is given to pattern testing for each cycle.

An object of the present invention is to provide a means for comparing and determining whether a pattern generated by a pattern generator is normal or abnormal for each cycle.

[Means for solving problems]

The above purpose is to focus on the patterns generated by the pattern generator, find out the regularity between the currently generated pattern and the previously generated patterns, and use the relationship as the expected value. , which was intended to enable inspection for each cycle, and includes a means for temporarily holding the currently generated pattern and the previously generated pattern, and a method for performing arithmetic 2# logical operations between these two patterns and outputting them. means for calculating the expected value of the calculation result, expected value storage means for storing the expected value of the calculation result, means for comparing the calculation means and the expected value storage means to determine whether they match or do not match, and means for storing all the signals when they do not match. This can be achieved by providing

[Effect]

A register is used to hold the current pattern generated by the pattern generator, and a register is used to hold patterns generated before the current pattern, and a pattern is loaded into the register every cycle. Next, arithmetic and logical operations are performed on the outputs of the two registers and the results are output. By comparing this with the expected value every cycle, a match or a mismatch is outputted to determine whether the pattern is normal or abnormal.

Since each operation is a basic operation of a logic circuit, there is no possibility of malfunction.

〔Example〕

A first embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

This will be explained with reference to FIG.

The configuration of the first embodiment includes a pattern generator 1. A register 2 that holds the current pattern generated by the pattern generator 1. A register 3 that holds the pattern before the current pattern, an arithmetic logic circuit 4 that performs arithmetic and logic operations on the output values of registers 2 and 3, an expected value register 5 that holds the expected value of this output, and an arithmetic logic circuit 4 that holds the expected value of this output. A comparison circuit 6 compares the outputs of the logic operation circuit 4 and the expected value register 5 and determines whether they match or not (if the results match, it is normal and no pulse is output; if the results do not match, it is abnormal and outputs an H pulse) , according to the output of the comparison circuit 6, the flip 70 knob 7 (
'0'' is normal, 11' is abnormal).

FIG. 2 is an example of a time chart when the pattern generator 7 generates a normal pattern, and FIG. 3 is an example of a time chart when the pattern generator 7 generates an incorrect pattern in the third cycle. Here, when the comparator circuit 6 is unstable (until the first cycle), a reset signal is output to the 7 Rig Hub 7.

Adaptation in which the pattern is correctly mapped will be described below with reference to FIGS. 1 and 2.

The first clock inputs the pattern @0'' generated from the pattern generator 1 into the register 2. The second clock inputs the pattern @0'' from the register 2, and the register 2 inputs the pattern. The arithmetic logic circuit 4 receives the pattern 11'' from the generator 1.
The output value of the register 3 is subtracted from the value @1'', and the result is output to the comparator circuit 6.

Here, the expected value register 5 holds 1" as an initial value. The comparison circuit 6 is an arithmetic logic operation circuit 40 output 11
It is compared and determined that the output of the expected 1st direct register 5 is ``1''.Therefore, it can be seen that the flip 70 knob is in the @0'' state and the shiba turn is normal. The third clock causes register 3 to output register 2 @1
", and at the same time register 2 receives "2".

The arithmetic logic operation circuit 4 subtracts the output value of the register 5 from the register 2 and outputs the result 11'' to the comparison circuit 6.The comparison circuit 6 compares this output "1" with the output "1" of the expected value register 5. It is compared and determined that `` is a match. Since the pattern is found to be normal, the 7 lip 7a knob 7 is in the state of @0''. Continue this series of movements until the end of the pattern. In the example time chart of FIG. 2, the pattern is normal, so the 7 rip 7 o knob remains @On until the end.

Next, the operation when an erroneous pattern is generated will be explained using FIGS. 1 and 3. Here, an example of an erroneous Shiba turn is a case where the pattern in the third cycle is erroneously changed from @2'' to 10''.

The first clock inputs the pattern @IO" generated from the pattern generator 1 into the register 2. The second clock causes the register 3 to receive the output value of the register 2.
mO" is fetched 9, and register 2 fetches the next pattern @1". The arithmetic logic operation circuit 4 subtracts the output value of the register 3 from the register 2 and outputs the result @1'' to the comparison circuit 6. The comparison circuit 6 subtracts this output value @1''' and the output value of the expected value register 5 '1''. ” is a match.

Therefore, 7 register 7a is in the state of 0''. At the fifth clock, register 5 outputs the output 12 of register 2.
”, register 2 is pattern 1 of the 3rd cycle.
As a result, the arithmetic logic circuit 4 subtracts the output value of register 3 from register 2 and obtains the result '''.
-1'' is output to the comparator circuit 6. The comparator circuit 6 compares and determines that this output value @-1'' and the output value @1'' of the expected value register 5 do not match, and outputs an H A pulse is output and flip 70 knob 7 is set to @1111.As a result, it can be seen that an incorrect pattern has been generated at the 5th tick.

As described above, when a mismatch is output, it can be easily seen that an incorrect pattern has been generated.

In this way, it has become possible to discover erroneous patterns that could not be discovered during pattern generation using the prior art.

In the first embodiment, the patterns from the pattern generator 1 are arranged in ascending order (the difference between the current and previous pattern is @1, so there is no need to change the expected value register 5. As an example, a case where the expected value changes every cycle will be explained with reference to FIGS. 3 and 6.

The second embodiment is obtained by adding a counter 8 and an expected value memory 9, which is a memory for storing expected values, to the configuration diagram of the first embodiment.

The operation of the second embodiment will be explained below.

11@ is set in the counter 8 in advance.

Further, in the second embodiment, the arithmetic and logic operation circuit 4 has a subtraction function. When the comparator circuit 6 is unstable (in the first cycle), a reset signal is output to the 7r lip 7r:1 tube 7.

At the first clock, the register 2 receives @0'' generated from the pattern generator 1. At the same time, the counter 8 counts up to @0'' and the expected value memory 9
The contents of address 0, @1", are read out. At the second clock, register 5 is @0", and register 2 is read out.
takes in @1” respectively.

Next, the arithmetic logic operation circuit 4 operates from register 2 to register 5.
A value obtained by subtracting the output value of is output to the comparator circuit 6. Also,
The expected value register 5 also takes in the output value 11" of the expected value memory 9 by the second link, and the counter 8 also receives @1"K.
It will be counted up. The comparison circuit 6 determines that the output "'1" of the expected value register 5 and the output @1" of the arithmetic logic operation circuit 4 match, and the flip-flop 7 outputs @0".
You can see that it is normal if it is in this state. 3rd glue a
The third register 3 takes in "1" and the register 2 takes in @0.The arithmetic logic circuit 4 subtracts the output value of register 3 from register 2 and sends the result "m-1" to the comparison circuit 6. At the same time, in the previous cycle, the contents of the first address, 11'', are read from the expected value memory 9, and the expected value register 5 is fetched and compared at the third clock. Output to circuit 6.

The comparator circuit 6 determines that the two human forces match. Therefore, it can be seen that the flip 70 knob 7 maintains the "lo" state and the pattern is normal.

Thereafter, the Shibataan test is executed to the end using the same operation. In the time chart example of FIG. 6, the pattern is normal, so there is no abnormality until the end. However, in the second embodiment, if an incorrect pattern is generated, the same procedure as in the first embodiment will be applied. The h0 pattern can be discovered by the determination method.

In a second embodiment, between the generated patterns,
Even if no regularity is found, color/li8
By providing an expected value memory 9, etc., the expected value can be generated.

Next, as a third embodiment, an example in which the first and second embodiments are applied to facilitate inspection of patterns generated by the pattern generator 1 will be described with reference to FIG.

When the pattern generated by the pattern generator 1 becomes complex, one inspection circuit (for example, the embodiment in FIG. 1) is used.
In this case, it is usually difficult to generate an expected value. However, according to the third embodiment, some kind of regularity is discovered from the pattern generated from the pattern generator, and as many test circuits (11, 12, etc.) as are necessary for that purpose are used. By providing a 10-karat gold control section, pattern calibration can be simplified.

According to the third embodiment, complex patterns can be easily inspected.

Three embodiments have been described above, and the first embodiment. The expected value generation method described in the second embodiment is not limited to the method using only registers or memory, but can also be generated using kakunta or the like. Furthermore, in arithmetic logic operation circuits, not only subtraction but also other logical operations (
(absolute value of addition, subtraction of two numbers) is also possible.

〔Effect of the invention〕

According to the present invention, it is possible to inspect all patterns generated by a pattern generator), and if an error occurs in a pattern, it can be detected at the time the error occurs even while the pattern is being generated. A pattern generator for semiconductor testing equipment can be realized.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of the first embodiment of the present invention, and FIG. 2 is a configuration diagram of the first embodiment of the present invention.
Fig. 3 is an example of a time chart when the first embodiment malfunctions, and Fig. 4 is a time chart of a pattern that is output multiple times by the pattern generator of Fig. 3. , FIG. 3 is a configuration diagram of the second embodiment, FIG. 6 is a time chart during normal operation of the second embodiment, and FIG.
The figure is a configuration diagram of the third embodiment. 1...Pattern generator, 2-...Register,
3...Register, 4...Arithmetic logic operation circuit, 5...Expected value register, 6...Comparison circuit, 7
...Flip-flop, 8...Cuff/ri, 9.
・・Expected value memory, 10−・Control circuit, 11・
...Test circuit, 12...Test circuit.

Claims (1)

[Claims] 1. In a pattern generator that generates test patterns for testing semiconductor LSIs, etc., a first storage means for temporarily storing and holding a pattern previous to the pattern currently generated by the pattern generator, the pattern generation means, and the first storage means; an arithmetic and logic operation means that performs an arithmetic and logic operation between the patterns output by the first storage means; a second storage means that stores and holds an expected value of the result of said operation; and an output of said second storage means and said arithmetic and logic operation. Comparing means for comparing the outputs of the means and third storage means for storing the discrepancy signal outputted from the comparing means are provided to facilitate the determination of whether or not the pattern is being generated normally. Characteristic pattern generator.