JPS6175275A - Pattern generator - Google Patents

Abstract

PURPOSE:To determine whether the operation is normal or not, by determining the cumulatively computed value over all addresses generated from the start to the end during the operation of an address generator to be compared with the expected value in the generation of normal address for inspection after the end of the operation. CONSTITUTION:A clock is supplied to an address generator 1 and a register 4 to operate the entire circuit based on it as reference. Addresses generated from the generator 1 by the first cycle of clock are fed to A of an adder 3 while the contents of a register 4 are provided to B of the adder 3 to add up and the results are outputted to the input side of the register 4. In response to the second cycle of clock, the results of the addition are brought into the register 4 and at the same time, the subsequent addresses are generated from the generator 1 to be fed to A of the adder 3. Such an adding operation is repeated to the end signal and the results are compared with the data of an expected value register 5.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a testing device for logic LSI, and particularly to a theory under test]! ! Highly reliable, which generates test patterns for lLSI.
Concerning test pattern generators.

[Background of the invention]

Generally, in logic LSI tests, the logic LSI which is the device under test is
Apply the test pattern to the SI input terminal.

The output value of the device under test in response to the input is compared with the expected output value to determine whether it is a good product or a defective product.

For final testing in the actual LSI production process.

Test equipment must operate correctly at all times.

If the test equipment malfunctions, not only will correct test results not be obtained, but in the worst case, a defective product may be determined to be a good product, which is extremely inconvenient. Therefore, in order to obtain correct test results, it is necessary to know whether the test device always operates correctly, or at least after the test is completed, whether or not the test device operated correctly during the test.

The present invention relates to means for determining whether or not a pattern generated by a test pattern generator of a test device is correct.The prior art will be described below with reference to FIG.

FIG. 1 shows a test pattern generator.

The pattern memory 2 is a large-capacity memory that stores test patterns to be applied to the logic LSI I0 under test, and according to the address generated by the address generator 1, the test pattern stored at that address is read out and generated. The pattern memory 2 is composed of test patterns and parity pits. The parity pits are used to determine whether or not the read pattern is normal.

However, conventionally, the addresses generated by the address generator 1 have only been inspected for the start address and the end address, and addresses generated in the middle have not been inspected. However, in recent years, as semiconductors have become highly integrated, LSIs with advanced functions have appeared, and testing thereof requires a large number of test patterns, and the generation of test patterns also needs to be faster. In particular, due to high-speed operation, the operation timing margin in the address generator is minimized, and inspection of the addresses generated by the address generator 1 has become important. In addition, as test patterns become longer, a large number of patterns are generated in one test, but if only the start address and end address are inspected, it is difficult to detect errors even if the addresses generated in the middle are incorrect. There is a problem that.

In other words, with the generation of a large number of patterns at high speed,
Some means of making it possible to check the addresses generated by the address generator has become necessary.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a means for checking all addresses generated from an address generator at high speed to determine whether the pattern generator is operating normally.

[Summary of the invention]

While the address generator is operating, calculate the cumulative calculation value for all addresses generated from the start address to the end address, and after the operation is finished, compare it with the expected cumulative calculation value when a normal address is generated. or abnormality.

[Embodiments of the invention]

The configuration of the first embodiment will be explained below using FIG. 2.

As shown in FIG. 2, the first embodiment includes an address generator 1
an adder 3 that treats the addresses generated from the register as numerical values and calculates the cumulative value of all generated addresses; a register 4 that temporarily holds the cumulative value output from the adder 3; A comparison circuit 6 that compares the cumulative addition value with an expected cumulative addition value in the case of normal operation, and an expected value register 5 that outputs the expected cumulative addition value to the comparison circuit 6.
It consists of The address generator 1 is designed to generate addresses by a microprogram.

The operation of the first implementation column will be explained in detail below with reference to FIGS. 2, 3, and 4.

In FIG. 2, a clock is supplied to an address generator 1 and a register 4, and the entire circuit operates based on this clock.

FIG. 3 is an example of a time chart when the address generated by the address generator 1 in FIG. 2 is accurately generated. In FIG. 3, address generator 1 generates address #2 using the first cycle clock and supplies the address to adder 3 A. In FIG. Content #0 of register 4 is given to B of adder 3. Adder 3 performs an addition operation on addresses #0 and 2 supplied to A and B, and outputs the addition result #2 to the input side of register 4. By the clock of the second cycle, 2, which is the result of the calculation, is taken into the register 4. At the same time, the address generator 1 generates the next address #4 and supplies it to the adder A of the adder 3. The output of the register 4 is given to B of the adder 3. The adder 3 performs an addition operation of 2 and #4 supplied to A and outputs the result 6 to the register 4.

The output 6 of the adder 3 is taken into the register 4 by the third cycle clock. At the same time, address generator 1 outputs the next address #9.

As described above, the address generator 1 outputs the END signal at the end address where the addition operation is repeated from the start address to the end address.

The contents of register 4 at this time are the cumulative results of all addresses, which is 44 in this time chart.

The comparison circuit compares the data in register 4 and the data in expected value register 6 at the timing of the END signal,
Make a judgment, the judgment in this case is normal, so NO
RMAL is output as a judgment output.

It can be seen that the address including the intermediate address was normal.

Figure 4 is an example of a time chart when the address generator outputs an incorrect address during operation.
It is assumed that address #6 is erroneously generated at normal address #4 in the cycle. Address #2 is generated from the address generator 1 by the first cycle clock and is supplied to A of the adder 3. The output O of the register 4 is given to the B of the adder 3. Adder 3 performs addition operation of 0 and #2 supplied to A and B,
The result, 2, is supplied to register 4.

By the clock of the second cycle, the register 4 takes in 2, which is the result of the Caro calculation. At the same time, the next address #4 should be generated from the address generator 1, but due to a malfunction, an incorrect address #6 is generated, and the address #6 is supplied to A of the adder 3.

Adder 3 performs an addition operation of 2 and #6 supplied to A and outputs the result 8 to register 4. By the third cycle clock, register 4 takes in the addition result #8.Similar to FIG. It is held at 4. Further, an expected cumulative value 44 is given from the 1 expected value register 5. In this case, the comparison circuit 6 determines that the cumulative result from the register 4 is different from the expected cumulative value, and outputs a 1 determination output ABNORM.

If ABNORM is output, this indicates that an erroneous address has been generated, and in this time chart, the erroneous address generated by the second cycle clock has been issued.

Therefore, according to the present invention, it is now possible to discover erroneous addresses during address generation, which could not be discovered by simply checking the start address and end address.

5, 6 and 7 show a second embodiment. The second example is a problem specific to logic LSI testers. This takes address offset processing into consideration. Address offset processing will be described below, followed by the configuration and operation of the second embodiment.

FIG. 5 shows an example of a test pattern for a ffff car and its reading order. The test pattern in FIG. 5 consists of five patterns, and the reading order is TPO→T.
P3→TP4→TPI→TP2. If this test pattern is stored from address 0 in the pattern memory,
The read address generated by the address generator is #
0 → #3 → #4 → #1 → #2, and the expected cumulative value of 1 is o
+3+4+1+2=10.

However, it is common to store a plurality of test patterns in the pattern memory at the same time, and it is rare that the test pattern shown in FIG. 5 is actually stored from address 0 in the pattern memory. for example.

When stored from address 20, the address generated by the address generator is #20 → #23 → #24 → 321 → #2
2 and the expected cumulative value is 20+23+24+21+22
=110. In other words, even if the test pattern is the same, there is a problem in that the expected cumulative value differs depending on the storage address.
This is extremely inconvenient for ≠ stars.

Therefore, in the second embodiment, by using an offset register 7 and a subtracter 8, only the start address is subtracted from the address generated by the address generator, and the result is returned to a relative address unique to the test pattern. This prevents the expected cumulative value from changing depending on the address.

The configuration of the second embodiment will be explained using FIG. 6.

FIG. 6 shows an address generator 1, a pattern memory 2, an offset register 7 that holds the first address where a test pattern to be generated is stored, and a subtracter for subtracting the contents of the offset register 7 from the generated address. 8, adder 3, register 4, expected value register 5, and comparison circuit 6
It is composed of:

The operation of the second embodiment will be explained below using FIGS. 6 and 7. FIG. 7 is a time chart representing the circuit operation of FIG. 6.

The offset register 7 holds the start address of the test pattern in advance.The first cycle clock causes the address generator 1 to select the start address #2.
0 is given to A of the subtractor 8.

B of the subtracter 8 is given the contents of the offset register 7. The subtracter 8 performs the calculation A-B using #20 and 20 given to A and B, and supplies the result of the operation 0 to the adder A of the adder 5. Thereafter, the subtracter 3 subtracts the value of the offset register 7 for each address generated by the address generator 1, and outputs the result to the adder 3.

In the adder 5, as in the first embodiment, the register 6 is used to perform one or more cumulative additions every cycle.
Even if the address where the test pattern is stored is different, the first address is subtracted by the subtracter 8.
The expected cumulative value will always have a constant value.

FIG. 8 shows a third embodiment. This is logic L
This takes into account the problem unique to SI testers: instruction J, which has an undefined number of execution cycles.

An instruction with an undetermined number of execution cycles is an instruction that applies a test pattern to the LSI under test and waits until the output of the LSI under test matches the expected output. Repeat until the output of matches the expected output.

Repeatedly generates the same address. Therefore, even if the test pattern is the same, there is a problem in that when an instruction with an undefined number of execution cycles is read out, the one expected cumulative value differs depending on the number of cycles.

Therefore, in the third embodiment, a detector 9 is provided to detect an instruction with an indefinite number of execution cycles, and the output of this detector is used to inhibit the addition operation in the adder 3 or update the data in the register 4. In other words, the cumulative addition of addresses is prohibited until the output of the LSI under test and the first period special output match, and the expected cumulative value of 1 is fixed.

As shown in FIG. 8, the configuration of the third embodiment is as follows.

It is composed of an address generator 1, a pattern memory 2, a detector 9 for detecting instructions with an uncertain number of execution cycles, an adder 3, a register 4, an expected value register 5, and a comparison circuit 6.

FIG. 9 is a time chart showing an example of the operation shown in FIG.

The address from the address generator is #2 → #4 → #9 → #
Let us consider the case where the numbers are generated in the order of 10→#7→#12. Here, it is assumed that an instruction whose execution cycle number is not determined corresponds to address #10. In FIG. 9, addresses other than address #10 are cumulatively added in the same manner as in the first embodiment. When address #10 is generated,
The detector 9 detects that the instruction has an indefinite number of execution cycles. This detection output inhibits cumulative addition in the adder 3 and register 4. Address #10 is repeatedly generated until the output of the LSI under test matches the expected output. During this time, no cumulative addition of addresses is performed, and no matter how many times address lO is generated, no cumulative addition is performed.

Based on the above operation, in the third embodiment, the cumulative addition of addresses corresponding to instructions whose execution cycle number is not determined is prohibited, and the expected cumulative value of 1 is fixed.

As described above, in the third embodiment, a detector for "instructions with an undetermined number of execution cycles" is used, but other methods are also conceivable. FIG. 1O shows a fourth embodiment.

In the fourth embodiment, the number of bits of the microprogram control memory 12 inside the address generator 1 is increased, a control command for the adder 3 is stored in the added bit 13, and the control command for the adder 3 is stored together with the control command for the address. This is read out, decoded by the decoder 14, and an instruction is given to the adder 3 as to whether or not to perform addition. As a result, if the instruction to inhibit addition of adder 3 is stored in additional bit 13 together with the "instruction with an undefined number of execution cycles", no matter how many cycles it takes for the "instruction with an undefined number of execution cycles", the expected The cumulative value can be fixed.

In the above embodiments, the explanation has been given by limiting the cumulative calculation to cumulative addition by addition calculation, but the present invention is not limited to this. The arithmetic unit may perform subtraction, or shift/rotate the added value (2x, 4x, 1)
You can do it twice...).

Shifting a value obtained by performing a logical operation (exclusive OR, etc.) between specific bits between a register value and an address value, etc.
Various accumulation operations are possible. In addition, the second example and the third example
The embodiments may be used in combination.

As described above, in this embodiment, not only the start address and the end address but also all addresses generated at high speed are checked, and each time an LSI test is completed, it is possible to know whether the test was normal or not. A pattern generator for LSI test equipment can be realized.

〔Effect of the invention〕

According to the present invention, not only the start address and the end address but also all addresses generated at high speed are inspected, and each time an LSI test is completed, it is possible to know whether the test was normal or not. A pattern generator of a test device can be realized.

[Brief explanation of the drawing]

Fig. 1 is a conventional circuit diagram, Fig. 2 is a configuration diagram of the first embodiment of the present invention, Fig. 3 is a time chart side port of the first embodiment during normal operation, and Fig. 4 is a diagram of the second embodiment. The side opening of the time chart at the time of malfunction in the embodiment, FIG. 5 is one storage side opening in the pattern memory,
FIG. 6 is a block diagram of a second embodiment of the present invention, FIG. 7 is a side view of the time chart of the second embodiment, FIG. 8 is a block diagram of a third embodiment of the present invention, and FIG. 9 is a block diagram of a third embodiment of the present invention. A side view of the time chart of the third embodiment, and FIG. 10 is a configuration diagram of the fourth embodiment. 1.Addresser, 2..Pattern memory, 3..
・Adder, 4...Register, 5...Expected value register, 6...Comparison circuit, 7...Offset register, 8
. . . Subtractor, 9 . . . Detector, 14 . . . Adder control command decoder. Agent Patent attorney Tadashi Akimoto Younger brother 1 Figure 2 Figure 3 System distribution Figure 4 εND I wording 7) ABNQRP'
1 Goen 44 Figure 5 H0ter〉 / Shiso Figure 6 Figure 7 Kuro・1 Rikuzu 1° Figure 8 Figure 9 Exit to 10, signal

Claims (1)

[Claims] 1. A pattern generator comprising an address generating means for generating an address, and a memory for storing a test pattern and successively generating a test pattern according to the generated address,
Within a predetermined pattern generation section, means for cumulatively adding up the addresses generated by the address generation means from the start to the end of pattern generation, and a means for cumulatively adding up addresses generated by the address generation means at the end of pattern generation and when a normal address is generated. A pattern generator comprising means for comparing the expected cumulative value with an expected cumulative value to determine whether or not the address generated by the address generating means is normal. 2. The pattern generator according to claim 1, wherein the address generation by the address generation means is performed by a microprogram. 3. The pattern generator according to claim 1, wherein the cumulative addition means cumulatively adds a value obtained by subtracting a fixed offset address from the address of the address generation means. 4. The pattern generator according to claim 2, wherein when the address generation means generates an address by a specific micro-instruction, the address during execution of the micro-instruction is prohibited from accumulating operations. . 5. The pattern generator according to claim 4, wherein the inhibition of the accumulation operation is executed by part of data of a microinstruction.