JPH0236378A - Fault diagnostic method for logic package - Google Patents

Abstract

PURPOSE:To shorten the time required for a diagnosis by supplying a self-test enable signal and a self-test clock signal to plural integrated circuits in common, and actuating the self-testing mechanism of the respective integrated circuits for the fault diagnosis. CONSTITUTION:A logic tester control part 1 holds the self-test enable signal 5 at level '1' first. Then the control part 1 supplies self-test clock signals 6a and 6b to start the self-testing mechanisms of the LSIs 4a-4c, thereby generating dummy random numbers as the test pattern of an LSI internal logic circuit and compressing the data of the output of the logic circuit corresponding to the test pattern. The final obtained compressed data are read out by scan circuits incorporated in the LSIs 4a-4c and set out as result signals 7a-7c of the fault diagnosis to a logic tester comparison part 2. The comparison part 2 compares the signals 7a-7c with the previously found expected values to judge whether or not the LSIs 4a-4c mounted on a logic package 3 are normal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for diagnosing failures in logic packages, and more particularly to a method for diagnosing failures in logic packages equipped with a plurality of integrated circuits each having a built-in self-test mechanism.

[Conventional technology]

Conventionally, failure diagnosis of logic packages equipped with a large number of integrated circuits (LSIs) with built-in self-test mechanisms has been carried out using logic simulators or by hand, using test patterns that are effective for detecting failures in integrated circuits and output expectations corresponding to the test patterns. For each integrated circuit, the test pattern is input in sequence to each integrated circuit using a logic tester, and the normality of the integrated circuit is determined based on whether the response signal matches the expected output value. This was done by running it sequentially.

For fault diagnosis of this type of logic package, see 1.
For example, it is discussed on pages 123 to 132 of Nikkei Electronics (published June 20, 1983).

[Problem to be solved by the invention]

In the above conventional technology, diagnostic operations such as applying a test pattern and comparing response signals with expected values are sequentially performed on each integrated circuit mounted on the package, so the time required for diagnosing a package failure is shortened. , which is the sum of the diagnostic time for each individual integrated circuit.

The problem was that it was going to be big.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fault diagnosis method that solves the problems of the prior art and reduces the time required to diagnose a logic package in which a plurality of integrated circuits are mounted.

[Means to solve the problem]

The above object is to commonly supply a self-test enable signal and a self-test clock signal to the plurality of integrated circuits in diagnosing the failure of a logic package equipped with a plurality of integrated circuits (logic LSIs) each having a built-in self-test mechanism; This is accomplished by simultaneously operating the self-test mechanisms of each integrated circuit to perform fault diagnosis.

[For production]

Each self-test mechanism of a plurality of integrated circuits mounted on a logic package simultaneously executes fault diagnosis using a common self-test enable signal and self-test clock signal inputted from a logic tester control unit, etc., and each self-test result signal is output from each self-test mechanism. Output. The logic tester comparison section compares each self-test result signal with a predetermined expected value to determine the normality of each integrated circuit.

In this way, by simply inputting a self-test control signal from the logic tester control section, the self-test mechanisms of each integrated circuit operate simultaneously and perform fault diagnosis, making it possible to shorten the time required to diagnose faults in logic packages. becomes.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a logic tester control section, 2 is a logic tester comparison section, 3 is a logic package to be diagnosed, 4a to 4c are logic LSIs having a self-test mechanism, 5 is the self-test mechanism enable signal, 6a
, 6b are self-test clock signals, and 7a to 7c are self-test result signals.

When diagnosing a fault in the logic package 3, the logic tester control unit 1 first sets the self-test enable signal 5 to "1". This self-test enable signal 5 is a common enable signal for the self-test mechanisms included in each of the LSIs 4a to 4c of the logic package 3, and unless this signal is in the #III state, each self-test mechanism will not operate. next,
A self-test clock signal 6a from the logic tester control unit 1;
6b, the self-test mechanisms of LSIs 4a to 4c start operating simultaneously, and sequentially generate pseudo-random numbers that serve as test patterns for the LSI's internal logic circuits, and sequentially perform data compression of logic circuit outputs corresponding to the test patterns. Note that the test clock signal 6a is for data input, and the test clock signal 6b is for data output.

The final compressed data obtained in this way is
Reading is performed by a scan circuit built in I4a-4c, and sent to logic tester comparator 2 as failure diagnosis result signals 7a-7c. The logic tester comparator 2 determines the normality of each LSI 4a-4c mounted on the logic package 3 by comparing the fault diagnosis result signals 7a-7c with expected values determined in advance.

FIG. 2 shows a configuration example of the logic LSI 4a in which the logic circuit to be subjected to failure diagnosis is configured by a combination that does not include flip-flops.
a~8h are logic LSI input signals, 9a~9h are logic LS
I output signal, 1o is a test pattern generation circuit, 11 is a combinational logic circuit to be fault diagnosed, and 12 is a data compression circuit.

The configurations of the logic LSIs 4b and 4c are also similar.

During normal operation, self-test enable signal 5 is “O”
In this case, the combinational logic circuit 11 operates according to the input signals 8a to 8h, and output signals 9a to 9h are obtained. On the other hand, when diagnosing a fault, the self-test enable signal 5 is
By becoming e 1 #, the input signals 8a to 8h are suppressed, and the output signal of the test pattern generation circuit 10 is applied as a test pattern to the combinational logic circuit 11 according to the test clock signal 6a. The data compression circuit 12 also outputs output signals 9a to 9h sequentially outputted from the combinational logic circuit 11 in accordance with the test clock signal 6b.
When the final compressed data is obtained, it is sent as a self-test result signal 7a by the built-in scan circuit.

FIG. 2 shows a configuration example for a case where a logic circuit to be subjected to failure diagnosis of a logic LSI does not include a flip-flop, and is not applicable to a case where a flip-flop is included in the logic circuit.

A configuration in which a flip-flop is included in the target logic circuit for fault diagnosis is, for example, IEEE, Te5tConfere.
nce (1979) pp. 37-41, and the explanation will be omitted.

FIG. 3 shows an example of the configuration of the test pattern generation circuit 10.
13a to 13h are flip-flops, and 14a to 14c are EOR logic circuits. The test pattern generation circuit is composed of a type of shift register called a linear feedback shift register, and feedback lines come out from certain flip-flops (13b, 13c, 13d in the example of FIG. 3), and there are FOR, take logic.

When this linear feedback shift register has an m-bit configuration, it can generate (2"-1) different bit patterns. In other words, each pattern can generate (2"-1) different bit patterns.
) appears only once in the cycle.

In order for this m-bit linear feedback shift register to generate a (2''-1) periodic pattern, the feedback line must be output from a certain position, but the value of m and the position of the feedback are determined by coding theory. Figure 3 shows an example of an 8-bit linear feedback shift register, with flip-flops 13a to 1
If you extract 8-bit parallel data from 3h,
An 8-bit parallel pseudo-random number with a period of (2''-1) is obtained, which can be applied to the internal logic circuit as a test pattern during fault diagnosis.

FIG. 4 shows an example of the configuration of the data compression circuit 12.
13p is a flip-flop, and 14d to 14n are FOR logic circuits. That is, the data compression circuit 12 also uses a linear feedback shift register similar to that used in the test pattern generation circuit 10. FIG. 4 shows a circuit for compressing a parallel data series to 8 bits. The data series uses FOR logic with the feedback line and enters the linear feedback shift register. One parallel data is input every shift clock, and the contents of the linear feedback shift register when all the parallel data series have been input are This is the final compressed data.

According to the embodiment shown in FIG. 1, the failure diagnosis of the LSIs 4a, 4b, and 4c mounted on the logic package 3 can be performed simultaneously, so that the time required for failure diagnosis can be shortened.

In addition, although the method of fault diagnosis using a logic tester was shown in the embodiment, the present invention can also be implemented by providing a configuration in which a common control signal can be given to the logic package even when it is installed in a data processing device. - Since the self-test mechanism within the LSI becomes operational, fault diagnosis of the logic package can be performed.

In addition, in the embodiment, the compressed data created by the LSI self-test mechanism is read by the scan circuit and compared with the expected value of 1 in the logic tester comparison section, but the expected value is held within the LSI by a combination of logic circuits. It is also possible to compare the data with the compressed data and output only the result. In this case, the fault diagnosis time can be further shortened.

〔Effect of the invention〕

As explained above, according to the present invention, fault diagnosis can be performed by simultaneously operating the self-test mechanisms built in a plurality of integrated circuits mounted on a logic package using the same control signal, thereby reducing the time required for fault diagnosis. can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A diagram showing an example of the configuration of the logic LSI in the figure.
A diagram showing an example of the configuration of the test pattern generation circuit in the figure,
FIG. 4 is a diagram showing an example of the configuration of the data compression circuit in FIG. 2. DESCRIPTION OF SYMBOLS 1... Logic tester control part, 2... Logic tester comparison part, 3... Logic package, 4a-4c... Logic LSI (logic element). 5... Self-test enable signal, 6a, 6b...
- Self-test clock signal, 7a to 7c... Self-test result signal. Figure ■ Figure 2 Figure 3

Claims (1)

[Claims] (1) When diagnosing the failure of a logic package equipped with a plurality of logic elements each having a built-in self-test mechanism, a self-test enable signal and a self-test clock signal are commonly supplied to the plurality of logic elements, and each logic element is A method for diagnosing a fault in a logic package, characterized by diagnosing a fault by simultaneously operating a self-test mechanism.