JP3101503B2 - Successive approximation type AD converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation type A / D conversion circuit, and more particularly to a circuit for simplifying measurement in a test.

[0002]

2. Description of the Related Art Generally, when evaluating a successive approximation type AD converter, it is necessary to examine the offset, non-linearity, and monotonous increase of a comparator. In particular, R as an internal DA converter
When a -2R ladder resistor network is used, the variation in resistance and the offset of the comparator affect the conversion error. For this reason, conventionally, an AD converter is operated by sequentially changing an applied analog voltage, and an error is determined by observing the conversion result at each change.

[0003]

In the successive approximation type AD conversion circuit, the conversion speed is determined in proportion to the bit width for AD conversion and the reference clock, and the conversion speed can be increased by increasing the reference clock. Can be shortened. However, in the successive approximation type AD conversion circuit, since the D / A conversion is once performed internally and the conversion result is compared with the applied analog voltage by a comparator, these processes take a considerable time, and the reference clock is extremely reduced. There was a problem that the speed could not be increased, and if the speed was forcibly increased, the conversion error would increase. Therefore, much time was required to obtain sufficient accuracy in the test.

[0004]

SUMMARY OF THE INVENTION The present invention provides a successive approximation register in which digital signals are sequentially set, a DA converter for converting the output of the successive approximation register from digital to analog, an output of the DA converter and an input analog signal. And a data latch that latches the output of the successive approximation register, and a comparator that outputs a comparison result to the successive approximation register. A first selector for selectively outputting one of a signal and an output of the comparator, and transmitting a digital signal input from the first external terminal to the successive approximation register during a test; This object is achieved by providing a second selector for leading an output to a second external terminal.

The present invention further comprises a third selector for leading the output of the DA converter to a third external terminal.

[0006]

According to the present invention, the digital signal input from the first external terminal can be directly set in the successive approximation register through the first selector during the test, and the comparison result of the comparator can be stored in the second successive selector through the second selector. 2 It is possible to output from an external terminal, and it is possible to evaluate from an input digital value, an applied analog signal, and an output comparison result.

Further, since the output of the internal D / A converter can be derived from the third external terminal via the third selector, if the analog voltage applied and the D / A conversion result output from the third external terminal are viewed, the comparator Can also be evaluated.

[0008]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Reference numeral 1 denotes a successive approximation register in which a digital signal as a comparison value is set; A D / A converter constituted by a -2R ladder resistor network, 3 is a comparator for comparing the output of the D / A converter 2 with the input analog signal A / DIN and outputting a comparison result COMPOUT, and 4 is an output of the successive approximation register 1 RD0-R
A data latch for latching D5, 50 to 55 are external terminals for outputting the respective bit outputs Q0 to Q5 of the data latch 4, and 6 is a timing generating circuit for supplying a clock signal to the successive approximation register 1.

[0009] The timing generation circuit 6 receives the reference clock C
A counter 7 comprising three T-type flip-flops operated by K, and 3-8 for converting the 3-bit outputs A, B, and C of the counter 7 into 8-bit timing signals Y0 to Y7.
A decoder 8 and AND gates 90, 91, 92, 93, 94, and 95 each having one end to which the decode output signals Y1 to Y6 are input and the other end receiving the reference clock CK, and sequentially comparing the outputs of the respective AND gates Latch circuits 100, 101, 102, 103, which constitute each bit of the register 1,
The clock signals are input to clock terminals 104 and 105. The inverted Q output of each bit of the successive approximation register is output to the NOR gate 20 together with the corresponding timing signals Y6 to Y1.
0, 201, 202, 203, 204, and 205, respectively, and output to buffers 300, 301, 302, 303, and 3
The data is input to each bit of the R-2R ladder resistance network 2 via the input lines 04 and 305.

Further, output lines 500, 501, 502, 503, 50 for outputting each bit of the data latch 4
4, 505, output buffers 600, 601, 60
2, 603, 604 and 605 are inserted, and the output of the NAND gate 20 for inputting the data output control signal OE and the test signal TEST is applied to the control terminal.

Next, a specific configuration of the present embodiment will be described. That is, in this embodiment, the external terminal 55 and the DA
The output end of the converter 2 is connected by a signal line 21,
A transmission gate 22, which is turned on only when the test signal is at the H level, is inserted into this signal line 21,
The gate 2 and the output buffer 605 make the selector 2
3 are configured. On the other hand, the external terminal 54 is connected to the output terminal of the comparator 3 by a signal line 24. An output buffer 25 that is turned on only when the test signal is at the H level is inserted into this signal line. The buffer 604 forms the selector 26.

The external terminal 53 is connected to a signal line 27 for inputting a digital signal from outside.
This input digital signal has two AND gates and one O
An input digital signal from the external terminal 53 is selected at the time of testing, an output of the comparator 3 is selected at normal times, and the selected signal is input to the successive approximation register 1. Is done.

The operation of this embodiment will be described below with reference to the timing charts of FIGS. First, when the counter 7 operates according to the reference clock CK, as shown in FIG. 2 to FIG. 2, timing signals Y1 to Y7 which sequentially become L level for one cycle of the reference clock CK are output.

During normal operation, the selector 28 controls the comparator 3
2 is selected and applied to the input of the successive approximation register 1, so that the comparison result (FIG. 2) is sequentially changed according to the timing signals Y1 to Y7 as shown in FIG. The latched result is latched by one of the latch circuits 105 to 100, and the comparison between the output obtained by DA conversion of the latch result and the input analog voltage is sequentially repeated. here,
Since the number of bits of the successive approximation register 1 is 6 bits, DA
The conversion and comparison operations are repeated six times, and the digital value of the successive approximation register 1 is determined.
The data is latched by the data latch 4 according to the output of the D gate 90. When the output control signal OE goes low, as shown in FIG.
All the output buffers 600 to 605 inserted in the data latch 4 are turned on, and the respective bit outputs Q0 to Q5 of the data latch 4 are output D0 to D5 as shown in FIG.
Will be output to

On the other hand, at the time of testing, the selector 28 selects the digital signal input to the external terminal 53 and inputs it to the successive approximation register 1, so that the serial data RD5, RD4, RD3, as shown in FIG. RD2
When RD1 and RD0 are input, these data are stored in the latches 105, 104, 10 and 10 of the successive approximation register 1 according to the timing signals Y1, Y2, Y3, Y4, Y5, and Y6.
3, 102, 101, and 100 are set. Since this setting does not involve the DA conversion and comparison operations unlike the related art, it is performed in a very short time, and by using a clock faster than that in the normal operation as the reference clock CK,
The time can be further reduced.

In addition to the setting of the digital signal, an analog signal corresponding to the set digital signal is output to the comparator 3.
, The comparator 3 compares the conversion result obtained by converting the set digital value with the DA converter 2 with the input analog voltage. During the test, the output buffer 25 is turned on and the output buffer 604 is turned off in the selector 26, so that the output COMPO of the comparator 3 is connected to the external terminal 54.
The UT is output, and the Q4 output of the data latch 4 is not output to the external terminal 54. In the selector 23, the transmission gate 22 is turned on and the output buffer 605 is turned off at the time of the test, so that the conversion result of the DA converter 2 is directly output to the external terminal 55 via the signal line 21.

By changing the input digital signal and analog signal and repeating the same operation, the conversion error and the offset of the comparator 3 can be measured, and the AD converter can be evaluated.

[0018]

According to the present invention, the evaluation time can be greatly reduced while maintaining the evaluation accuracy of the AD converter. Moreover, even the offset of the internal comparator can be measured. Therefore, it is possible to reduce the test cost and the product unit price.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing a normal operation in the embodiment.

FIG. 3 is a timing chart illustrating a test operation in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Successive approximation register 2 DA converter 3 Comparator 4 Data latch 50-55 External terminal 6 Timing generation circuit 7 Counter 8 Decoder 21, 24 Signal line 23, 26, 28 Selector

Claims (2)

(57) [Claims] 1. A successive approximation register in which digital signals are sequentially set, a DA converter for DA-converting the output of the successive approximation register, and comparing the output of the DA converter with an input analog signal and comparing the comparison result with the input analog signal. In a successive approximation type AD conversion circuit having a comparator for outputting to a successive approximation register and a data latch for latching an output of the successive approximation register, a digital signal input from a first external terminal and an output of the comparator are output. A first selector for selectively outputting any one of them and sending a digital signal input from the first external terminal to the successive approximation register at the time of a test, and leading an output of the comparator to a second external terminal at the time of a test And the output of the DA converter to a third external terminal.
A successive approximation type A / D conversion circuit comprising a third selector for deriving the A / D converter. 2. A timing for further generating a clock signal.
A single output from the first selector.
Data from the line is synchronized with the clock signal timing.
Sequentially set in the successive approximation register based on
2. The successive approximation type AD conversion circuit according to claim 1, wherein