JPH10163873A - Successive approximation a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a digital signal of (m+1) bits with a resistance number of a serial resistance network that is conventionally needed to acquire a digital signal of (m) bit resolution. SOLUTION: When the most significant bit of a 9-bit digital signal is set in a data register 15, almost intermediate voltage VZ and analog voltage are compared by a comparator 14, and the comparison result is set as the most significant bit in a data register 15 through a successive approximation circuit 16. Either P or N-channel MOS transistors 4 or 5 is simultaneously turned on by a control signal CTL from the circuit 16 at this time, both ends of a serial resistance circuit network 1 are connected to AV+ or AV- and its intermediate voltage ((AV+)-(AV-))/2, and after that, residual eight bits are successively compared in and approximated in a range of both end voltages of the network 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation type A / D converter suitable for realizing (m + 1) -bit resolution with the number of resistors having an m-bit resolution.

[0002]

2. Description of the Related Art In a successive approximation type AD converter, a so-called m-type converter for converting an analog voltage into an m-bit digital signal.
In order to provide bit resolution, a reference is usually made to a series resistor network in which 2 m resistors are connected in series between two different power supplies, and a voltage obtained from a predetermined connection point of the series resistor network. A comparator that outputs a bit signal of “1” or “0” as compared with an analog voltage as a voltage and an m-bit register in which the output of the comparator is set in order from the most significant bit to the least significant bit are required. The connection point of the series resistor network is sequentially changed according to the output result of the comparator.

[0003] Now, a higher resolution is required, and an AD converting from m bits to (m + 1) bits digital signal is required.
When creating a converter, a series resistor network of 2
It is necessary to change the number of resistances of the (m) th power to the number of resistances of the power of 2 (m + 1). For example, in the case of an AD converter with an 8-bit resolution, the number of resistors in the series resistor network is 256, but if an AD converter with a 9-bit resolution is to be realized, 512 resistors are required, which is twice as large. The number of resistors in the series resistor network will increase significantly with higher bit resolution.

[0004]

SUMMARY OF THE INVENTION The above successive approximation type AD
When integrating a converter, the resistors that make up the series resistor network determine the size of the integrated circuit. Therefore, simply increasing the bit resolution by one bit increases the number of resistors by a factor of two, and increases the chip area, which inevitably leads to an increase in cost as the number of elements increases. However, there was a problem that the applicability was reduced.

Therefore, the present invention provides a successive approximation type AD converter in which the number of resistors in the series resistor network is only the number of resistors having an m-bit resolution even when the bit resolution is increased by one bit from m bits to (m + 1) bits. The purpose is to provide.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the feature of the present invention is that an analog voltage is successively compared with a plurality of reference voltages to obtain a signal having a m.
A necessary number of resistors are connected in series to obtain a bit digital signal, and one end has a first voltage and a second voltage smaller than the first voltage.
A series resistance network to which an intermediate voltage is applied, a switch circuit for selectively applying one of the first voltage and the second voltage to the other end of the series resistance network, and the analog voltage And a reference voltage generated from a predetermined connection point of the series resistor network to output a bit signal of “1” or “0”; and detecting the state of the output of the comparator to obtain the reference voltage. A detection circuit that outputs a control signal for connecting the switch circuit to either one of the first and second voltages, when the signal is an intermediate voltage between the first and second voltages; Or, after being connected to one of the second voltages, the voltage at any one connection point of the series resistor network is selectively output as a reference voltage according to the state of the control signal and the output of the comparator. A selection output circuit, the output of the comparator is provided with a data register are sequentially set the most significant bit to least significant bit, and in that for converting the analog voltage to the (m + 1) bit digital signal.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit block diagram showing a successive approximation type AD converter of the present invention. The case where the successive approximation type AD converter of FIG. 1 is built in a microcomputer will be described below.

In FIG. 1, (1) is a series resistor network, in which 2 @ m-1 resistors having a resistance value R are connected in series, and a resistor is connected across the series resistor having the resistance value R to both ends. It is obtained by connecting two resistors having a value of R / 2 in series. For example, in the case of a successive approximation type AD converter for obtaining a 9-bit digital signal, the number of resistors is 257. FIG. 2 shows the characteristics of analog-digital conversion when the number of resistors is 257. The microcomputer is provided with power supply terminals (2) and (3) for applying a voltage to the series resistance network (1), and the power supply terminals (2) and (3) have the first voltage AV + and the first voltage AV +, respectively. A second voltage AV- lower than one voltage is applied. One end of a series resistance network (1) and a power supply terminal (2)
Is connected to the drain-source path of the P-channel MOS transistor (4), and is connected between one end of the series resistance network (1) and the power supply terminal (3). ), The P-channel type and N-channel type MOS transistors (4) and (5) are turned on and off complementarily by one output of a successive approximation circuit to be described later, and the series resistance network (1). Is connected to one of the power supply terminals (2) and (3). Also, at the other end of the series resistance network (1),
The output terminal of a voltage follower type operational amplifier (6) is connected. The operational amplifier (6) has a negative terminal connected to its output terminal and a positive terminal connected to a resistor (7) having a resistance value R.
It is connected to the connection point of (8). Where the resistance (7)
A first voltage AV + and a second voltage AV- are applied to both ends of (8), that is, ((AV +)-(AV-)) / 2 is applied to the other end of the series resistance network (1). First voltage AV
+ And the intermediate voltage between the second voltage AV−. Here, the reason for using the voltage follower type as the operational amplifier (6) is that a constant voltage can be output even when the resistance values of the respective resistors constituting the series resistance network (1) fluctuate or vary. This is because it has characteristics. When the P-channel MOS transistor (4) is turned on, the series resistance network (1) has the first voltage AV + at both ends.
And the intermediate voltage ((AV +)-(AV-)) / 2, that is, the intermediate voltage ((AV +)-(AV-)) / 2 is applied to each connection point of the series resistance network (1). A voltage obtained by dividing the above voltage appears. On the other hand, when the N-channel MOS transistor (5) is on, the series resistance network (1) has the second voltage AV− and the intermediate voltage ((AV +) − (AV
−)) / 2, ie, a series resistor network (1)
Are connected to the intermediate voltage ((AV +) − (AV
−)) / 2 or less voltage appears.

The reason why a resistor having a resistance value of R / 2 is connected to both ends of the series resistor network (1) will be described with reference to the characteristic diagram of FIG. In FIG. 2, the horizontal axis represents an analog voltage to be AD-converted, and the vertical axis represents an AD voltage corresponding to the analog voltage.
It represents the digital value after conversion. Further, in the characteristic diagram of FIG. 2, a, b, c,... On the horizontal axis correspond to voltages appearing at connection points a, b, c,... Of the series resistance network (1). The connection point of the series resistance network (1) is 1
By shifting to the next adjacent connection point, the least significant bit of the digital value changes by +1 or -1. Here, if the solid straight line indicating the analog signal intersects the middle point of the broken staircase wave indicating the digital value, the analog voltage can be surely converted into the corresponding digital value, so that both ends of the series resistance network (1) Is connected to a resistor having a resistance value of R / 2 for offsetting. The area on the left side of the dashed line is N
The case where the channel type MOS transistor (5) is on is shown.
This is the case where the OS transistor (4) is on.

Reference numeral (9) denotes 2 m transmission gates, and each connection point of the series resistance network (1) is connected to its gate input / output. A control circuit (10) is connected to the control terminals of all the transmission gates (9), and selectively opens one of the transmission gates (9) based on the successive comparison result. is there. The detailed operation will be described later.

(11) is an analog input switching circuit,
This is for switching and outputting an analog signal applied to any one of eight analog input terminals AD0 to AD7 provided in the microcomputer. (12) is a 3-bit channel register, which has analog input terminals AD0 to AD0.
The 3-bit data for selecting any one of AD7 is A
When performing the D conversion, the data bus (1) is read in accordance with the result of decoding the program data read from the ROM (not shown).
Set via 3). The analog input switching circuit (11) has a decoding format in which any one of the analog input terminals can be selected according to the contents of the channel register (12). For example, if the contents of the channel register (3) are “000”, “001”, “010”, “01”
1 ”,“ 100 ”,“ 101 ”,“ 110 ”,“ 111 ”, the analog input terminals AD0, AD1, AD2, A
The internal wiring of the analog input switching circuit (11) is connected so that D3, AD4, AD5, AD6, and AD7 are selected. Reference numeral (14) denotes a comparator, which is provided at a predetermined connection point of the series resistance network (1) and obtained from a reference voltage obtained through a transmission gate (9) connected to the predetermined connection point and an analog input switching circuit (11). The voltage value of one output analog signal is compared, and when the analog signal is higher than the reference voltage, the logic “1” is output, and when the analog signal is lower than the reference voltage, the logic “0” is output. Things. (15) is a 9-bit data register. Nine digital values of "1" or "0" sequentially obtained from the comparator (14) are transmitted from the most significant bit (MSB) side through a successive comparison circuit described later. These are sequentially set toward the least significant bit (LSB). Specifically, although not shown, the data register (15) is provided with nine latch circuits corresponding to each bit from the most significant bit to the least significant bit. The output terminal of the comparator (14) through the successive approximation circuit is commonly applied to the input terminal of the "1" or "0" output, and each clock input terminal of the latch circuit is provided with a counter (not shown). A gate circuit is provided for opening a gate for clock input using an output of a decoder for decoding a numerical value. That is, a gate circuit is provided for each clock input terminal of each latch circuit, a clock is commonly applied to one input of each gate circuit, and the decoder is provided to the other input. For example, when the digital value of the most significant bit is output from the comparator (14), the wiring of the decoder is arranged so that the clock is applied only to the latch circuit corresponding to the most significant bit of the data register (15). ing.

Reference numeral (16) denotes a successive approximation circuit, which is controlled by an AD conversion instruction register described later so as to perform an operation of sequentially setting the output of the comparator (14) from the most significant bit to the least significant bit of the data register (15). Controlled. (19) is a latch circuit, and the comparison result of the comparator (14) is stored in the L (latch) terminal by the successive approximation circuit (1).
6), and the C (clock) terminal is connected to the latch circuit corresponding to the most significant bit as a result of decoding the counting result of the counter when setting the digital value to the most significant bit of the data register (15). The clock CK to be applied is applied to the clock input terminal. Also, R
The EOC signal is inverted and applied to the (reset) terminal. This EOC signal is decoded by the CPU of the microcomputer via the data bus (13) when the A / D conversion instruction register sets data indicating the end of the A / D conversion operation from the successive approximation circuit (16). And
It becomes "0". When the A / D conversion operation is started, the successive approximation circuit (16) starts the A / D conversion operation in response to the other set contents which are subjected to the A / D conversion.
The signal becomes "1".

(20) and (21) are NAND gates constituting an RS flip-flop. One input of the NAND gate (20) serving as a set terminal of the RS flip-flop has * Q (inverted output) of the latch circuit (19). ) Terminal, and an EOC signal is applied to one input of a NAND gate (21) serving as a reset terminal. The output of the NAND gate (21), which is the output of the RS flip-flop, is applied as a control signal CTL to one input of the EXOR gate (17), and the P-channel MOS transistor (4) and the N-channel MOS transistor (5) ) Are commonly applied to the gates. A digital value applied to the data register (15) is applied to the other input of the EXOR gate (17). The EXOR gate (17) is provided between the control signal CTL and the comparator (14).
The exclusive-OR operation is performed with the output, and the control circuit (10) is controlled by the operation output to open any one of the transmission gates (9). As described above, the successive approximation circuit (16) is controlled by the AD conversion instruction register (18). That is, ROM
The program data read from the program is a content for executing the A / D conversion, and data for starting the A / D conversion in the A / D conversion instruction register (18) via the data bus (13) based on the result of decoding the program data. Is set, the successive approximation circuit (16) starts operating according to the contents of the AD conversion instruction register (18) at this time. That is, the successive approximation circuit (16) operates so as to sequentially set the digital value output and applied one bit at a time from the comparator (14) from the most significant bit to the least significant bit of the data register (15). I do. A 9-bit digital value is applied from the comparator (14) to the successive approximation circuit (16), that is, the data register (15).
When the 9-bit digital signal after the analog signal AD conversion is set to the analog signal, data indicating that the AD conversion operation has been completed is output from the successive approximation circuit (16) and set in the AD conversion instruction register (18). The contents of the AD conversion instruction register (18) at this time are decoded by the CPU via the data bus (13). The data register (1
The 9-bit digital signal set in 5) is transferred to the data bus (13), and is logically operated by the CPU for a predetermined purpose.

The operation of FIG. 1 will be described below. First, when the execution of the AD conversion operation is started based on the result of decoding the program data read from the ROM, one of the analog input terminals AD0 to AD7 is selected according to the set contents of the channel register (12). Then, the analog voltage applied to the selected analog input terminal is applied to the + terminal of the comparator (14). On the other hand, AD
In the initial state of the conversion operation, since the EOC signal is "1", the output of the NAND gate (21) constituting the RS flip-flop becomes "1", that is, the control signal CTL.
Becomes "1", the N-channel MOS transistor (5) is turned on, and the series resistance network (1) is connected between the intermediate voltage ((AV +)-(AV-)) / 2 and AV-. You. In the initial state, the series resistance network (1)
Only the transmission gate (9) connected to the connection point Z is turned on, so that the minus terminal of the comparator (14) has a substantially intermediate voltage (hereinafter referred to as VZ) at the connection point Z of the series resistance network (1). Is applied. For example, when the analog voltage is higher than the voltage generated at the connection point Z of the series resistance network (1), the output of the comparator (14) becomes “1”,
This "1" output is set to the most significant bit of the data register (15) via the successive approximation circuit (16) in synchronization with the clock CK. At the same time, the most significant bit "1" is also latched by the latch circuit (19) in synchronization with the clock CK, and the output of the NAND gate (21) constituting the RS flip-flop, that is, the control signal CTL becomes "0". Therefore, the N-channel MOS transistor (5) turns off and the P-channel MOS transistor (5) turns on. Thus, the series resistance network (1) is connected to the first voltage AV.
+ And the intermediate voltage ((AV +) − (AV −)) / 2. Further, "1" is output from the EXOR gate (17), and the control circuit (10) receives this "1" output and activates the transmission gate (9) located between the first voltage AV + and the intermediate voltage. Open the transmission gate (9) as a reference voltage ((A
V +)-VZ) / 2 is output to the comparator (14).
Is applied to the-terminal. Then, the data register (1
In order to determine the digital value of the upper 8 bits of 5), the analog voltage at this time and the reference voltage ((AV +)-VZ) /
2 will be compared next by the comparator (14). For example, if the analog voltage is equal to the reference voltage ((AV +) −
When the voltage is lower than (VZ) / 2, the output of the comparator (14) becomes "0", so that the output of the EXOR gate (17) becomes "0", and the voltage ((AV +)-VZ) / 2 and the voltage VZ A transmission gate (9) that generates an intermediate voltage between the two is opened by the control circuit (10), and the intermediate voltage ((AV +) − VZ) / 4 is applied as a reference voltage to the − terminal of the comparator (14). Data register (1
“0” is set in the upper 8 bits of 5). Hereinafter, this successive approximation operation is performed until data is set in the least significant bit of the data register (15). As a result, 9-bit data is set in the data register (15).

In the above example, the case where the P-channel MOS transistor (4) is turned on has been described. However, the N-channel MOS transistor (5) is turned on, and the second voltage is applied across the series resistor network (1). AV- and ((AV +)
− (AV −)) / 2, a 9-bit digital value can be obtained by the same operation. As described above, in the embodiment of the present invention, in the initial state of the AD conversion,
The intermediate voltage VZ is applied to the comparator (14) as a reference voltage to obtain the most significant bit of the digital value.
One of the channel type MOS transistor (4) and the N-channel type MOS transistor (5) is turned on so that one end of the series resistance network (1) is connected to the first voltage AV + or the second voltage AV-. Therefore, even when a 9-bit resolution digital signal is obtained, the number of resistors of the series resistor network (1) required for 8-bit resolution can be sufficiently satisfied. As a result, the number of elements can be minimized, the cost can be suppressed, and the chip size can be reduced, so that it is possible to sufficiently cope with small electronic devices.

[0016]

According to the present invention, even when a digital signal having (m + 1) -bit resolution is obtained, a series resistor network having the number of resistors conventionally required for m-bit resolution can be used. The number of resistors can be reduced. As a result, it is possible to suppress an increase in cost and an increase in chip size, and to obtain an advantage that it can sufficiently cope with a small electronic device.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a successive approximation type AD converter of the present invention.

FIG. 2 is a characteristic diagram showing characteristics of the successive approximation type AD converter of the present invention.

[Explanation of symbols]

 (1) Series resistor network (4) P-channel MOS transistor (5) N-channel MOS transistor (14) Comparator (15) Data register (16) Successive comparison circuit (17) EXOR gate

Claims (2)

[Claims] An analog voltage is successively compared with a plurality of reference voltages to obtain an m-bit digital signal. A necessary number of resistors are connected in series, and one end has a first voltage and a first voltage smaller than the first voltage. A series resistance network to which an intermediate voltage between the two voltages is applied; and the other end of the series resistance network, the first voltage or the second voltage.
A switch circuit for selectively applying one of the voltages, and comparing the analog voltage with a reference voltage generated from a predetermined connection point of the series resistance network, and outputting a bit signal of “1” or “0”. By detecting the state of the output of the comparator and the comparator,
When the reference voltage is an intermediate voltage between the first and second voltages,
A detection circuit that outputs a control signal for connecting the switch circuit to one of the first or second voltage, and after the switch circuit is connected to one of the first or second voltage, A selection output circuit for selectively outputting a voltage at any one connection point of the series resistance network as a reference voltage in accordance with a state of the control signal and an output of the comparator; A successive approximation type AD converter comprising: a data register that is sequentially set to lower bits; and converting the analog voltage into a (m + 1) -bit digital signal. 2. The selection output circuit, comprising: a gate circuit that performs a logical operation of the control signal and an output of the comparator; and a voltage at any one connection point of the series resistance network based on an output of the gate circuit. 2. The successive approximation type AD converter according to claim 1, further comprising a selection circuit for outputting the reference voltage.