JPH08102671A - Successive approximation type a/d conversion circuit - Google Patents

Abstract

PURPOSE: To sharply shorten evaluation time while holding the evaluation accuracy of an A/D converter and to measure also the offset of an internal comparator. CONSTITUTION: A successive approximation type A/D conversion circuit, provided with a successive approximation register 1, a D/A converter 2, a comparator 3, and a data latch 4, is also provided with a 1st selector 28 for selectively outputting either one of a digital signal inputted from a 1st external terminal 53 and the output of the comparator 3 and sending the digital signal inputted from the terminal 53 to the register 1 at the time of a test, a 2nd selector 26 for leading out the output of the comparator 3 to a 2nd external terminal 54 at the time of the test and a 3rd selector 23 for leading out the output of the D/A converter 2 to a 3rd external terminal 55. The A/D converter is evaluated based upon outputs from the 1st to 3rd external terminals, the input digital signal and an analog signal to be impressed to the comparator 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation type AD conversion circuit, and more particularly to the same circuit which simplifies measurement during a test.

[0002]

2. Description of the Related Art Generally, when evaluating a successive approximation type AD conversion circuit, it is necessary to examine the offset, non-linearity and monotonic increase of the comparator. Especially, as an internal DA converter, R
When using the -2R ladder resistor network, resistance variations and comparator offsets affect the conversion error. Therefore, conventionally, the analog voltage to be applied is sequentially changed to operate the AD converter, and the error is determined by observing the conversion result for each change.

[0003]

In the successive approximation type AD conversion circuit, the conversion speed is determined in proportion to the bit width for AD conversion and the reference clock, and the conversion speed can be increased by increasing the reference clock. Can be shortened. However, in the successive approximation type AD conversion circuit, since the DA conversion is once performed inside and the conversion result is compared with the applied analog voltage by the comparator, it takes a considerable amount of time for these processes, and the reference clock is extremely set. There is a problem in that it cannot be made faster, and if it is made faster, the conversion error becomes larger. Therefore, it took a lot of time to obtain sufficient accuracy in the test.

[0004]

According to the present invention, a successive approximation register in which digital signals are sequentially set, a DA converter for DA converting the output of the successive approximation register, an output of the DA converter and an input analog signal are provided. In a successive approximation type AD conversion circuit including a comparator for comparing the following and outputting a comparison result to the successive approximation register, and a data latch for latching the output of the successive approximation register, a digital input from a first external terminal A first selector that selectively outputs one of a signal and an output of the comparator and sends a digital signal input from the first external terminal to the successive approximation register during a test; and a comparator of the comparator during a test. The above problem is solved by providing a second selector for deriving an output to the second external terminal.

Also, the present invention provides a third selector for deriving the output of the DA converter to the third external terminal.

[0006]

In the present invention, at the time of test, the digital signal input from the first external terminal can be directly set in the successive approximation register through the first selector, and the comparison result of the comparator can be set through the second selector through the second selector. It becomes possible to output from the two external terminals, and it becomes possible to evaluate from the input digital value, the applied analog signal, and the output comparison result.

Further, since the output of the internal DA converter can be derived from the third external terminal through the third selector, the comparator can be obtained by looking at the applied analog voltage and the DA conversion result output from the third external terminal. The offset of can also be evaluated.

[0008]

1 is a block diagram showing the configuration of an embodiment of the present invention, in which 1 is a successive approximation register in which a digital signal as a comparison value is set, and 2 is an R for DA converting the output of the successive approximation register. A DA converter composed of a −2R ladder resistance network, a comparator 3 for comparing the output of the DA converter 2 with the input analog signal A / DIN, and outputting a comparison result COMPOUT, and a reference numeral 4 for the output of the successive approximation register 1. RD0-R
A data latch for latching D5, 50 to 55 are external terminals for outputting bit outputs Q0 to Q5 of the data latch 4, respectively, and 6 is a timing generating circuit for supplying a clock signal to the successive approximation register 1.

The timing generation circuit 6 has a reference clock C.
A counter 7 composed of three T-type flip-flops operated by K, and 3-8 for converting 3-bit outputs A, B, C of the counter 7 into 8-bit timing signals Y0 to Y7
It is composed of a decoder 8 and AND gates 90, 91, 92, 93, 94 and 95 each of which receives the decode output signals Y1 to Y6 at one end and the reference clock CK at the other end, and sequentially compares the outputs of the AND gates. Latch circuits 100, 101, 102, 103, which configure each bit of the register 1,
It is input to the clock terminals C of 104 and 105. Further, the inverted Q output of each bit of the successive approximation register is supplied to the NOR gate 20 together with the corresponding timing signals Y6 to Y1.
0, 201, 202, 203, 204, 205 respectively, and buffers 300, 301, 302, 303, 3
It is input to each bit of the R-2R ladder resistance network 2 via 04 and 305.

Further, output lines 500, 501, 502, 503, 50 for outputting each bit of the data latch 4
4, 505 have output buffers 600, 601, 60
2, 603, 604, and 605 are inserted, and the output of the NAND gate 20 for inputting the data output control signal OE and the test signal TEST is applied to the control terminals thereof.

Next, the specific structure of this embodiment will be described. That is, in this embodiment, the external terminal 55 and the DA
The output terminal of the converter 2 is connected by a signal line 21,
A transmission gate 22 which is turned on only when the test signal is at the H level is inserted in the signal line 21.
With this gate 22 and output buffer 605, the selector 2
3 are configured. On the other hand, the external terminal 54 is connected to the output end of the comparator 3 by the signal line 24, and an output buffer 25 that turns on only when the test signal is at the H level is inserted in this signal line. The buffer 604 constitutes the selector 26.

Further, a signal line 27 for inputting a digital signal from the outside is connected to the external terminal 53,
This input digital signal has two AND gates and one O
It is input to the selector 28 composed of an R gate. In this selector, the input digital signal from the external terminal 53 is selected during the test, the output of the comparator 3 is selected during the normal time, and the selected signal is input to the successive approximation register 1. To be done.

The operation of this embodiment will be described below with reference to the timing charts of FIGS. First, when the counter 7 operates according to the reference clock CK, as shown in FIGS. 2A to 2C, the timing signals Y1 to Y7 that sequentially become the L level for one cycle of the reference clock CK are output.

At the time of normal operation, the comparator 28 is operated by the selector 28.
2 is selected and is applied to the input of the successive approximation register 1, the comparison result (FIG. 2C) is shown in accordance with the timing signals Y1 to Y7 as shown in FIGS. No. 1 is latched by the latch circuits 105 to 100, and the comparison of the output obtained by DA conversion of the latched result and the input analog voltage is sequentially repeated. here,
Since the successive approximation register 1 has 6 bits, DA
The conversion and comparison operations are repeated 6 times to determine the digital value of the successive approximation register 1, and the determined digital value is AN.
It is latched by the data latch 4 according to the output of the D gate 90. Then, as shown in FIG. 2A, when the output control signal OE becomes L level, the output lines 500 to 50
2, all the output buffers 600 to 605 inserted in 5 are turned on, and the bit outputs Q0 to Q5 of the data latch 4 are output as D0 to D5 as shown in FIG.
Will be output to.

On the other hand, during the test, the selector 28 selects the digital signal input to the external terminal 53 and inputs it to the successive approximation register 1. Therefore, as shown in FIG. 3, the serial data RD5, RD4, RD3. RD2
When RD1 and RD0 are input, these data are transferred to the latches 105, 104 and 10 of the successive approximation register 1 in accordance with the timing signals Y1, Y2, Y3, Y4, Y5 and Y6.
It is set to 3, 102, 101, 100. Since this setting does not involve DA conversion and comparison operation unlike in the past, it is performed in an extremely short time, and by using a faster clock than the normal operation as the reference clock CK,
The time can be further shortened.

Along with the setting of the digital signal as described above, the comparator 3 outputs an analog signal corresponding to the set digital signal.
When the signal is input to one of the two, the conversion result obtained by converting the set digital value by the DA converter 2 and the input analog voltage are compared by the comparator 3. During the test, the output buffer 25 is turned on and the output buffer 604 is turned off in the selector 26, so that the output COMPO of the comparator 3 is connected to the external terminal 54.
UT is output, and the Q4 output of the data latch 4 is not output to the external terminal 54. Further, in the selector 23, since the transmission gate 22 is turned on and the output buffer 605 is turned off during the test, the conversion result of the DA converter 2 is directly output to the external terminal 55 via the signal line 21.

By changing the input digital signal and analog signal and repeating the same operation, the conversion error and the offset of the comparator 3 can be measured, and the AD converter can be evaluated.

[0018]

According to the present invention, the evaluation time can be significantly shortened while maintaining the evaluation accuracy of the AD converter. Moreover, even the offset of the internal comparator can be measured. Therefore, it becomes possible to reduce the test cost and the product unit price.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a timing chart showing a normal operation in the embodiment.

FIG. 3 is a timing chart showing a test operation in the example.

[Explanation of symbols]

 1 successive approximation register 2 DA converter 3 comparator 4 data latch 50-55 external terminal 6 timing generation circuit 7 counter 8 decoder 21, 24 signal line 23, 26, 28 selector

Claims (2)

[Claims] 1. A successive approximation register in which digital signals are sequentially set, a DA converter for performing DA conversion on the output of the successive approximation register, an output of the DA converter and an input analog signal are compared, and a comparison result is obtained. In a successive approximation A / D conversion circuit including a comparator for outputting to a successive approximation register and a data latch for latching the output of the successive approximation register, a digital signal input from a first external terminal and an output of the comparator are provided. A first selector that selectively outputs one of them and sends a digital signal input from the first external terminal to the successive approximation register during a test; and outputs the output of the comparator to a second external terminal during a test. And a second selector for performing the successive approximation AD
Conversion circuit. 2. The successive approximation type AD conversion circuit according to claim 1, further comprising a third selector for deriving an output of the DA converter to a third external terminal.