JPH046134B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to counter integrated circuits. Conventionally, when testing a single package using this type of counter integrated circuit (IC), all values that the counter can take are fixed by fixing all bits other than the bits that are changed by combining them with the values of other flip-flops. When testing a circuit that uses the output of this counter by providing the minimum required pattern, the counter value must be loaded in a parallel path or the required value must be created by counting up or down. If parallel paths cannot be provided, the use of count up/down is time consuming and
The drawback was that it was not easy to collect information in the event of a failure. SUMMARY OF THE INVENTION An object of the present invention is to provide a counter integrated circuit which overcomes the above-mentioned drawbacks. In order to achieve the above object, the present invention provides a counter integrated circuit with a shift function, in which a first stage circuit group includes a holding means, an input gate for outputting shift-in data in response to a shift instruction signal, and a first stage circuit group. A count-up gate for outputting the negative output of the holding means in response to a count-up instruction signal, and means for latching the output data from the count-up gate or the output data from the input gate to the holding means using a clock signal. The i-th (i≧2) stage circuit group includes a holding means;
a shift gate that outputs the output of the holding means at the i-1st stage in response to the shift instruction signal; a first count-up gate that logically ANDs the negative output of the holding means and the count-up instruction signal; A second count-up gate that performs logical AND with the instruction signal, output data from the shift gate, output data from the first count-up gate, or output data from the second count-up gate. and means for latching the shift instruction signal to the holding means using a clock signal, and during a count-up operation, the generation of the shift instruction signal is stopped to suppress the shift operation by the input gate and the shift gate, and during the shift operation, the shift instruction signal is latched to the holding means. The present invention is characterized in that the count-up operation by the count-up gate, the first count-up gate, and the second count-up gate is suppressed by stopping generation of the instruction number. Hereinafter, the present invention will be explained in more detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a counter integrated circuit according to the present invention. In the figure, 1-i (same for i=1 to 4) is a flip-flop that holds the current value, 3-i,
4-i, 5-i, 7-i and 8 are AND gates, 2-i is OR gate, 6 is NAND gate, 5
0-i is a load data signal line, 51 is a shift-in data signal line, 52 is a count-up instruction signal line, 53 is a shift register instruction signal line, 54 is a load instruction signal line, 55 is a clear instruction signal line, 56
is the clock signal line, 57 is the carry output signal line,
58-i indicates a data output signal line. In this embodiment, input gate 5 - 4 outputs shift-in data provided via shift-in data signal line 51 in response to a shift instruction signal provided via shift instruction signal line 53 . The count-up gate 4-4 outputs the negative output from the flip-flop 1-4 in response to a count-up instruction signal applied via the count-up instruction signal line 52. The OR gate 2-4 is connected to the load data signal line 50.
-4, the load data applied via the AND gate 3-4, the shift-in data output from the input gate 5-4, and the output from the count-up gate 4-4 are ANDed and the input data signal line 59- The input data is supplied to 4. Flip-flops 1-4 respond to a clock signal applied via clock signal line 56 to latch data on input data signal line 59-4. The second, third, and fourth stage circuit groups have slightly different configurations from the first stage circuit group. The circuit groups in the second and higher stages have the same configuration. Each of the circuit groups in the second stage and above is a flip-flop 1.
-3, 1-2, and 1-1. The shift gates 5-3, 5-2 and 5-1 are
The outputs of flip-flops 1-4, 1-3 and 1-2 located one stage below are outputted in response to a shift instruction signal applied via shift instruction signal line 53. First count-up gate 4-3, 4-2
and 4-1 are the outputs of the flip-flops 1-4, 1-3 and 1-2 located one stage below the relevant stage from the first stage, and the outputs of the flip-flops 1-3, 1-2 of the same stage.
AND the negative output of 1-1 and the count-up instruction signal applied via the count-up instruction signal line 52. Second count-up gate 7-3, 7-2
and 7-1 are the negative outputs of the first count-up gates 4-3, 4-2 and 4-1, and the flip-flops 1-3, 1-2 and 1-1 of the same stage.
1 and the count-up instruction signal applied via the count-up instruction signal line 52 are ANDed. When resetting the flip-flop 1-i, the clear instruction signal line 55 is set to "0" and a pulse is input to the clock signal line 56. Then, AND gate 3-i, 4-i, 5-i
Since all the signals at the output of 7-i are "0", the input data signal line 59 of the flip-flop
-i become all "0", and flip-flop 1-i is set to "0" at the rising edge of the clock signal. Next, when instructing to load data using a parallel path in order to give a certain value to the counter in advance, the signal on the count up instruction signal line 52 is set to "0", the signal on the clear instruction signal line 55 is set to "1", and the load instruction signal is set to "0". The signal on line 54 is set to "0" and a pulse is input to clock signal line 56. In this case, the AND gate 3-i is opened and the data on the load data signal line 50-i is output to the input signal line 59-i of the flip-flop, and the load data is set in the flip-flop 1-i at the rising edge of the clock signal. . To explain the operation when a load instruction is given using the waveform diagram in FIG. 2, the count-up instruction signal 52 signal is "0" and the shift instruction signal 53 signal is "0".
When the signal of the load instruction signal 54 is "0", the signals of the load data signal lines 50-1, 50-2, 50-3, and 50-4 are changed to the flip-flops 1-1, 50-4 at the rising edge of the clock pulse.
1-2, 1-3, and 1-4, respectively, and counter output signal lines 58-1, 58-2, 5
The corresponding values are output to 8-3 and 58-4. Furthermore, when counting up, the clear instruction signal line 55 is set to "1," the load instruction signal line 54 is set to "1," the shift instruction signal line 53 is set to "0," and the count up instruction signal line 52 is set to "1." A pulse is input to the clock signal 56. In this case, the first count up gate 4-
i, and second count-up gate 7-i
operates, and the value of the current value + 1 is set in flip-flop 1-i. In other words, if a 4-bit binary counter is arranged as shown in Table 1, the logic for counting up every clock is a3=3・(count-up condition) a2=(a3・2+3・a2)・(count-up condition) ) a1=(a1・a2・a3+a1・(a2・a3)) ・(count up condition) a0=(0・a1・a2・a3+a0・(1・2・3)) ・(count up condition) , first count-up gate 4-
i and the second count-up gate 7-i constitute a gate circuit that realizes these conditions.

[Table] Next, when performing a shift operation, set the shift instruction signal line 53 to "1" and set the count up instruction signal line 5 to "1".
2 is set to "0", the load instruction signal line 54 is set to "1", and the clear instruction signal line 55 is set to "1", and a pulse is input to the clock signal. In this case, the shift-in data signal passes through AND gate 5-4, passes through OR gate 2-4, and is set in flip-flop 1-4, and the outputs of flip-flops 1-1, 1-2, and 1-3 are ANDed. Gates 5-1, 5-2, and 5-
3 and or gate 2-1, 2-2, and 2-
3 to flip-flops 1-1, 1-2, and 1-3. Flip Flop 1-
A value of 1 may be used as other shift-in data. To explain using the waveform diagram at the time of shift instruction in FIG. 2, when the clear signal line 55 is "1", the load instruction signal line 54 is "1", and the count up instruction signal line 52 is "0", the shift instruction signal is Shift-in data signal line 51 and counter output signal lines 58-4, 58-3, and 58 at the rising edge of the clock pulse when line 53 is "1".
-2 outputs are flip-flops 1-4, respectively.
1-3, 1-2, and 1-1, and counter output signal lines 58-4, 58-3, 58-2,
and the signal 58-1 changes. By providing the shift function as described in detail above, the present invention has the effect of facilitating testing of a package or device using the counter integrated circuit of the present invention and easily collecting information in the event of a failure.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a counter integrated circuit according to the present invention. FIG. 2 is a waveform diagram for explaining the operation of the circuit of FIG. 1. 1-i...flip flop, 2-i...or gate, 3-i, 4-i, 5-i, 7-i, 8...
...And gate, 6...Nand gate.

Claims (1)

[Claims] 1. The first stage circuit group includes a holding means, an input gate that outputs shift-in data in response to a shift instruction signal, and a negative output of the holding means in response to a count-up instruction signal. an i-th (i≧2) stage, the i-th (i≧2) stage comprising: a count-up gate for outputting the count-up gate; and means for latching the output data from the count-up gate or the output data from the input gate to the holding means using a clock signal; The second circuit group includes: a holding means; a shift gate that outputs the output of the i-1st stage holding means in response to the shift instruction signal; a first logical product of the output of the holding means, the negative output of the i-th holding means, and the count up instruction signal;
a second count-up gate that calculates the AND of the negative output of the first count-up gate, the output of the i-th stage holding means, and the count-up instruction signal; and means for latching the output data from the shift gate, the output data from the first count-up gate, or the output data from the second count-up gate to the holding means by a clock signal, and performs a count-up operation. During the shift operation, the generation of the shift instruction signal is stopped to inhibit the shift operation by the input gate and the shift gate, and during the shift operation, the generation of the count-up instruction signal is stopped and the count-up gate and the first A counter integrated circuit with a shift function, characterized in that the count-up operation by the count-up gate and the second count-up gate is suppressed.