JPS5957347A - メモリアドレス制御装置 - Google Patents

メモリアドレス制御装置

Info

Publication number
JPS5957347A
JPS5957347A JP57169137A JP16913782A JPS5957347A JP S5957347 A JPS5957347 A JP S5957347A JP 57169137 A JP57169137 A JP 57169137A JP 16913782 A JP16913782 A JP 16913782A JP S5957347 A JPS5957347 A JP S5957347A
Authority
JP
Japan
Prior art keywords
address
register
gate
instruction
direct
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57169137A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6230653B2 (https=
Inventor
Takashi Sakao
坂尾　隆
Katsuhiko Ueda
勝彦 上田
Toshiaki Suzuki
敏明 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57169137A priority Critical patent/JPS5957347A/ja
Publication of JPS5957347A publication Critical patent/JPS5957347A/ja
Publication of JPS6230653B2 publication Critical patent/JPS6230653B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
JP57169137A 1982-09-27 1982-09-27 メモリアドレス制御装置 Granted JPS5957347A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57169137A JPS5957347A (ja) 1982-09-27 1982-09-27 メモリアドレス制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57169137A JPS5957347A (ja) 1982-09-27 1982-09-27 メモリアドレス制御装置

Publications (2)

Publication Number Publication Date
JPS5957347A true JPS5957347A (ja) 1984-04-02
JPS6230653B2 JPS6230653B2 (https=) 1987-07-03

Family

ID=15880966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57169137A Granted JPS5957347A (ja) 1982-09-27 1982-09-27 メモリアドレス制御装置

Country Status (1)

Country Link
JP (1) JPS5957347A (https=)

Also Published As

Publication number Publication date
JPS6230653B2 (https=) 1987-07-03

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