JPS5954951U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5954951U
JPS5954951U JP14874982U JP14874982U JPS5954951U JP S5954951 U JPS5954951 U JP S5954951U JP 14874982 U JP14874982 U JP 14874982U JP 14874982 U JP14874982 U JP 14874982U JP S5954951 U JPS5954951 U JP S5954951U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
metal plate
shielded
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14874982U
Other languages
Japanese (ja)
Inventor
名和田 一正
酒井 敏昭
光久 清水
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP14874982U priority Critical patent/JPS5954951U/en
Publication of JPS5954951U publication Critical patent/JPS5954951U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例である金属板を示す斜視図、
第2図は本考案の一実施例である絶縁チップを半導体の
パッケージのリードピンに装着した斜視図、第3図は本
考案の一実施例である金属板で遮蔽された半導体装置を
示す斜視図である。 図中1・・・・・・金属板、2・・・・・・貫通孔、3
・・・・・・半導体パッケージ、4・・・・・・リード
ピン、5・・・・・・絶縁チップ。
FIG. 1 is a perspective view showing a metal plate which is an embodiment of the present invention;
FIG. 2 is a perspective view of an insulating chip mounted on the lead pins of a semiconductor package, which is an embodiment of the present invention, and FIG. 3 is a perspective view of a semiconductor device shielded with a metal plate, which is an embodiment of the present invention. It is. In the figure 1...Metal plate, 2...Through hole, 3
... Semiconductor package, 4 ... Lead pin, 5 ... Insulation chip.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子を収容する基板に配設されるリードピンが絶
縁層を介して金属板により遮蔽されてなることを特徴と
する半導体装置。
A semiconductor device characterized in that lead pins arranged on a substrate housing a semiconductor element are shielded by a metal plate via an insulating layer.
JP14874982U 1982-09-30 1982-09-30 semiconductor equipment Pending JPS5954951U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14874982U JPS5954951U (en) 1982-09-30 1982-09-30 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14874982U JPS5954951U (en) 1982-09-30 1982-09-30 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS5954951U true JPS5954951U (en) 1984-04-10

Family

ID=30330392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14874982U Pending JPS5954951U (en) 1982-09-30 1982-09-30 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5954951U (en)

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