JPS5951529A - 相対位置検出パタ−ン - Google Patents

相対位置検出パタ−ン

Info

Publication number
JPS5951529A
JPS5951529A JP57162561A JP16256182A JPS5951529A JP S5951529 A JPS5951529 A JP S5951529A JP 57162561 A JP57162561 A JP 57162561A JP 16256182 A JP16256182 A JP 16256182A JP S5951529 A JPS5951529 A JP S5951529A
Authority
JP
Japan
Prior art keywords
pattern
patterns
position detection
relative position
interval
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57162561A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6348420B2 (enrdf_load_stackoverflow
Inventor
Kazuhiko Tsuji
和彦 辻
Masaru Sasako
勝 笹子
Koichi Kugimiya
公一 釘宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57162561A priority Critical patent/JPS5951529A/ja
Publication of JPS5951529A publication Critical patent/JPS5951529A/ja
Publication of JPS6348420B2 publication Critical patent/JPS6348420B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP57162561A 1982-09-17 1982-09-17 相対位置検出パタ−ン Granted JPS5951529A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57162561A JPS5951529A (ja) 1982-09-17 1982-09-17 相対位置検出パタ−ン

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57162561A JPS5951529A (ja) 1982-09-17 1982-09-17 相対位置検出パタ−ン

Publications (2)

Publication Number Publication Date
JPS5951529A true JPS5951529A (ja) 1984-03-26
JPS6348420B2 JPS6348420B2 (enrdf_load_stackoverflow) 1988-09-29

Family

ID=15756924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57162561A Granted JPS5951529A (ja) 1982-09-17 1982-09-17 相対位置検出パタ−ン

Country Status (1)

Country Link
JP (1) JPS5951529A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS633416A (ja) * 1986-06-24 1988-01-08 Sony Corp 半導体装置
WO2002082531A3 (en) * 2001-04-05 2003-02-27 Infineon Technologies Corp Structure and method for determining edges of regions in a semiconductor wafer
JP2009004601A (ja) * 2007-06-22 2009-01-08 Jeol Ltd 荷電粒子ビーム描画装置のフィールド接合精度測定方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH023217U (enrdf_load_stackoverflow) * 1988-06-20 1990-01-10

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS633416A (ja) * 1986-06-24 1988-01-08 Sony Corp 半導体装置
WO2002082531A3 (en) * 2001-04-05 2003-02-27 Infineon Technologies Corp Structure and method for determining edges of regions in a semiconductor wafer
US6828647B2 (en) 2001-04-05 2004-12-07 Infineon Technologies Ag Structure for determining edges of regions in a semiconductor wafer
JP2009004601A (ja) * 2007-06-22 2009-01-08 Jeol Ltd 荷電粒子ビーム描画装置のフィールド接合精度測定方法

Also Published As

Publication number Publication date
JPS6348420B2 (enrdf_load_stackoverflow) 1988-09-29

Similar Documents

Publication Publication Date Title
US5982044A (en) Alignment pattern and algorithm for photolithographic alignment marks on semiconductor substrates
JPH0831897A (ja) 半導体素子の重畳測定マーク及びこれを用いた半導体素子の多重パターン間の重畳誤差測定方法
JP2870461B2 (ja) フォトマスクの目合わせマーク及び半導体装置
JP3067732B2 (ja) 半導体装置のアライメント装置及びアライメント方法
JP2001093820A (ja) マーク、アライメントマーク、合わせずれ測定用マーク、フォトマスク、及び、半導体ウェーハ
JPS5951529A (ja) 相対位置検出パタ−ン
JP4040210B2 (ja) 露光方法、レチクル及び半導体装置の製造方法
US20030044057A1 (en) Method of checking overlap accuracy of patterns on four stacked semiconductor layers
JP2773708B2 (ja) 露光用マスク
JP3453793B2 (ja) 半導体装置及びこれを用いたアライメント検査方法
JPH07111952B2 (ja) ホトリソグラフィー工程におけるガラスマスク
JPH10189425A (ja) アライメント方法、アライメント精度測定方法及びアライメント測定用マーク
JPH1174189A (ja) マスクの位置ずれ検出用マーク
JPH0547621A (ja) 半導体製造プロセスにおけるマスク合わせ方法
KR19980043616A (ko) 포토마스크
JP2564440B2 (ja) ウエハ内位置表示を付したチップの製造方法
JPS588132B2 (ja) 集積回路製造方法
JPH0242741A (ja) 半導体装置
KR100223272B1 (ko) 중첩 오차 측정마크 및 이를 이용한 중첩 오차 보상방법
JP2977471B2 (ja) ウエハのアラインメントマークの配置方法
JPH04587B2 (enrdf_load_stackoverflow)
KR19990034619U (ko) 반도체 제조용 포토마스크
JPH0766113A (ja) レチクル及び位置合わせ用バーニアの形成方法
JP2513540Y2 (ja) アライメント測定装置
JP2000133572A (ja) 重ね合わせ精度測定用パターン