JPS59501646A - メモリ用直列デ−タ・モ−ド回路 - Google Patents

メモリ用直列デ−タ・モ−ド回路

Info

Publication number
JPS59501646A
JPS59501646A JP58502793A JP50279383A JPS59501646A JP S59501646 A JPS59501646 A JP S59501646A JP 58502793 A JP58502793 A JP 58502793A JP 50279383 A JP50279383 A JP 50279383A JP S59501646 A JPS59501646 A JP S59501646A
Authority
JP
Japan
Prior art keywords
data
output
signal
response
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58502793A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0412554B2 (en:Method
Inventor
レワンドウスキイ・アラン・ジエイムズ
モエンチ・ジエリ−・デ−ル
Original Assignee
モトロ−ラ・インコ−ポレ−テツド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by モトロ−ラ・インコ−ポレ−テツド filed Critical モトロ−ラ・インコ−ポレ−テツド
Publication of JPS59501646A publication Critical patent/JPS59501646A/ja
Publication of JPH0412554B2 publication Critical patent/JPH0412554B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
JP58502793A 1982-09-23 1983-07-29 メモリ用直列デ−タ・モ−ド回路 Granted JPS59501646A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/422,047 US4484308A (en) 1982-09-23 1982-09-23 Serial data mode circuit for a memory
US422047 2006-06-02

Publications (2)

Publication Number Publication Date
JPS59501646A true JPS59501646A (ja) 1984-09-13
JPH0412554B2 JPH0412554B2 (en:Method) 1992-03-04

Family

ID=23673177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58502793A Granted JPS59501646A (ja) 1982-09-23 1983-07-29 メモリ用直列デ−タ・モ−ド回路

Country Status (4)

Country Link
US (1) US4484308A (en:Method)
EP (1) EP0120033A4 (en:Method)
JP (1) JPS59501646A (en:Method)
WO (1) WO1984001230A1 (en:Method)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4567579A (en) * 1983-07-08 1986-01-28 Texas Instruments Incorporated Dynamic memory with high speed nibble mode
US4710866A (en) * 1983-09-12 1987-12-01 Motorola, Inc. Method and apparatus for validating prefetched instruction
US4757445A (en) * 1983-09-12 1988-07-12 Motorola, Inc. Method and apparatus for validating prefetched instruction
JPS61160898A (ja) * 1985-01-05 1986-07-21 Fujitsu Ltd 半導体記憶装置
US4845664A (en) * 1986-09-15 1989-07-04 International Business Machines Corp. On-chip bit reordering structure
CA2028085A1 (en) * 1989-11-03 1991-05-04 Dale J. Mayer Paged memory controller
US5383155A (en) * 1993-11-08 1995-01-17 International Business Machines Corporation Data output latch control circuit and process for semiconductor memory system
US5598376A (en) * 1994-12-23 1997-01-28 Micron Technology, Inc. Distributed write data drivers for burst access memories
US6804760B2 (en) 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US5682354A (en) * 1995-11-06 1997-10-28 Micron Technology, Inc. CAS recognition in burst extended data out DRAM
US5652724A (en) * 1994-12-23 1997-07-29 Micron Technology, Inc. Burst EDO memory device having pipelined output buffer
US6525971B2 (en) 1995-06-30 2003-02-25 Micron Technology, Inc. Distributed write data drivers for burst access memories
US5640364A (en) * 1994-12-23 1997-06-17 Micron Technology, Inc. Self-enabling pulse trapping circuit
US5610864A (en) * 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5668773A (en) * 1994-12-23 1997-09-16 Micron Technology, Inc. Synchronous burst extended data out DRAM
US5721859A (en) * 1994-12-23 1998-02-24 Micron Technology, Inc. Counter control circuit in a burst memory
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US5729503A (en) * 1994-12-23 1998-03-17 Micron Technology, Inc. Address transition detection on a synchronous design
US5675549A (en) * 1994-12-23 1997-10-07 Micron Technology, Inc. Burst EDO memory device address counter
US5717654A (en) * 1995-02-10 1998-02-10 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5850368A (en) * 1995-06-01 1998-12-15 Micron Technology, Inc. Burst EDO memory address counter
US5729504A (en) * 1995-12-14 1998-03-17 Micron Technology, Inc. Continuous burst edo memory device
US7681005B1 (en) 1996-01-11 2010-03-16 Micron Technology, Inc. Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
US5966724A (en) * 1996-01-11 1999-10-12 Micron Technology, Inc. Synchronous memory device with dual page and burst mode operations
JPH09288888A (ja) * 1996-04-22 1997-11-04 Mitsubishi Electric Corp 半導体記憶装置
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US5889979A (en) * 1996-05-24 1999-03-30 Hewlett-Packard, Co. Transparent data-triggered pipeline latch
US6981126B1 (en) 1996-07-03 2005-12-27 Micron Technology, Inc. Continuous interleave burst access
US6401186B1 (en) 1996-07-03 2002-06-04 Micron Technology, Inc. Continuous burst memory which anticipates a next requested start address
US6263448B1 (en) 1997-10-10 2001-07-17 Rambus Inc. Power control system for synchronous memory device
US7103742B1 (en) 1997-12-03 2006-09-05 Micron Technology, Inc. Burst/pipelined edo memory device
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222492A (ja) * 1982-06-19 1983-12-24 Mitsubishi Electric Corp 半導体メモリ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
US4079456A (en) * 1977-01-24 1978-03-14 Rca Corporation Output buffer synchronizing circuit having selectively variable delay means
US4106109A (en) * 1977-02-01 1978-08-08 Ncr Corporation Random access memory system providing high-speed digital data output
JPS5831674B2 (ja) * 1979-12-19 1983-07-07 株式会社日立製作所 メモリ
JPS5727477A (en) * 1980-07-23 1982-02-13 Nec Corp Memory circuit
US4344156A (en) * 1980-10-10 1982-08-10 Inmos Corporation High speed data transfer for a semiconductor memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222492A (ja) * 1982-06-19 1983-12-24 Mitsubishi Electric Corp 半導体メモリ

Also Published As

Publication number Publication date
EP0120033A4 (en) 1986-09-04
EP0120033A1 (en) 1984-10-03
JPH0412554B2 (en:Method) 1992-03-04
WO1984001230A1 (en) 1984-03-29
US4484308A (en) 1984-11-20

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