JPS5947845A - Ｃｍｏｓロジツクアレイ - Google Patents

Ｃｍｏｓロジツクアレイ

Info

Publication number
JPS5947845A
JPS5947845A JP57157466A JP15746682A JPS5947845A JP S5947845 A JPS5947845 A JP S5947845A JP 57157466 A JP57157466 A JP 57157466A JP 15746682 A JP15746682 A JP 15746682A JP S5947845 A JPS5947845 A JP S5947845A
Authority
JP
Japan
Prior art keywords
gate circuit
array
circuit
time
output line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57157466A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0137008B2 (enrdf_load_stackoverflow
Inventor
Junichi Iwasaki
岩先　純一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57157466A priority Critical patent/JPS5947845A/ja
Publication of JPS5947845A publication Critical patent/JPS5947845A/ja
Publication of JPH0137008B2 publication Critical patent/JPH0137008B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
JP57157466A 1982-09-10 1982-09-10 Ｃｍｏｓロジツクアレイ Granted JPS5947845A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57157466A JPS5947845A (ja) 1982-09-10 1982-09-10 Ｃｍｏｓロジツクアレイ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57157466A JPS5947845A (ja) 1982-09-10 1982-09-10 Ｃｍｏｓロジツクアレイ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP31788588A Division JPH0220924A (ja) 1988-12-16 1988-12-16 ロジックアレイ

Publications (2)

Publication Number Publication Date
JPS5947845A true JPS5947845A (ja) 1984-03-17
JPH0137008B2 JPH0137008B2 (enrdf_load_stackoverflow) 1989-08-03

Family

ID=15650281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57157466A Granted JPS5947845A (ja) 1982-09-10 1982-09-10 Ｃｍｏｓロジツクアレイ

Country Status (1)

Country Link
JP (1) JPS5947845A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208316A (ja) * 1985-03-12 1986-09-16 Asahi Micro Syst Kk プログラマブル論理回路
US4841174A (en) * 1985-10-21 1989-06-20 Western Digital Corporation CMOS circuit with racefree single clock dynamic logic

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208316A (ja) * 1985-03-12 1986-09-16 Asahi Micro Syst Kk プログラマブル論理回路
US4841174A (en) * 1985-10-21 1989-06-20 Western Digital Corporation CMOS circuit with racefree single clock dynamic logic

Also Published As

Publication number Publication date
JPH0137008B2 (enrdf_load_stackoverflow) 1989-08-03

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