JPS5947748A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPS5947748A
JPS5947748A JP57156649A JP15664982A JPS5947748A JP S5947748 A JPS5947748 A JP S5947748A JP 57156649 A JP57156649 A JP 57156649A JP 15664982 A JP15664982 A JP 15664982A JP S5947748 A JPS5947748 A JP S5947748A
Authority
JP
Japan
Prior art keywords
wire
lead
frame
loop
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57156649A
Other languages
Japanese (ja)
Inventor
Yoshiaki Hasegawa
長谷川　義昭
Minoru Imai
稔 今井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57156649A priority Critical patent/JPS5947748A/en
Publication of JPS5947748A publication Critical patent/JPS5947748A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To protect a wire from falling of frame and contacting of frame with jig and drastically reduce wire bending and defective wire touch by providing protrusion in such a manner as surrounding a wire loop in such a height higher than the wire loop. CONSTITUTION:A pellet (semiconductor element) 1 is fitted on a tab 2 and the pellet 1 and post leads 4, 5 are loop-connected by wire. Under this condition, protrusions 11, 12 which are higher than the height b of wire loop 7 are provided to the post leads 4, 5 in such a manner as surrounding rhe wire loop. Thereby, even when the lead frame has fallen with the surface facing to the pellet placed lower side, it is protected by protrusions 11, 12 and wire bending or wire touch can be prevented. The protrusions 11, 12 of post lead can be formed by bending a part of the end point of post leads 4, 5 at a right angle to the lead surface.

Description

【発明の詳細な説明】 本発明は半導体装置用のリードフレーム構造に関する。[Detailed description of the invention] The present invention relates to lead frame structures for semiconductor devices.

樹脂モールド半導体装置例えば樹脂モールドトランジス
タの組立においては、第１図に示すように半導体素子（
ペレット）１を取り付けるための金属タブ２を有するリ
ード３とそれ以外の複数のリード（ポストリード）４．
５とを一組として複数組のリード群をフレーム（枠）部
６と一体に形成したリードフレームが使われる。このリ
ードフレームの状態で第２図に示すようにタブ２へのベ
レット付はペレット１とリード４．５との間のＡＨ（又
はＡｔ）ワイヤ７によるｒツイヤボンディング及び樹脂
（同図に２点鎖線８で示す）モールドがなされる。When assembling a resin molded semiconductor device, such as a resin molded transistor, the semiconductor element (
A lead 3 with a metal tab 2 for attaching a pellet) 1 and a plurality of other leads (post leads) 4.
A lead frame is used in which a plurality of lead groups (5 and 5) are integrally formed with a frame portion 6. In this state of the lead frame, as shown in Fig. 2, attaching the pellet to the tab 2 is done by r-twier bonding with the AH (or At) wire 7 between the pellet 1 and the lead 4. A mold (indicated by a dotted chain line 8) is made.

このような樹脂モールドトランジスタの製造不良の一つ
としてワイヤの曲りやワイヤタッチ不良が問題となって
いる。これはトランジスタの組立や樹脂モールド工程に
お−て第３図に示すようにベレット付は後のリードフレ
ームを底部に溝９を有する治具１０に多数例文てかけた
状態で一時収納するが、フレームが同図矢印の方向に横
倒（−になってベレット付は側が下になるとき、ペレッ
トやポストリードよりも高くループ形状にも９上ったＡ
ｕ（Ａｔ）ワイヤ４が第２図の点線（７’　）で示すよ
うに曲りられペレッ）１との接触によυ知絡不艮を起丁
ことである。Wire bending and wire touch defects are one of the manufacturing defects of such resin-molded transistors. This is because during the transistor assembly or resin molding process, as shown in Fig. 3, the lead frame with a bellet is temporarily stored by hanging it over a jig 10 having a groove 9 at the bottom. When the frame falls sideways in the direction of the arrow in the same figure (-) and the side with the bullet is down, it is higher than the pellet or post lead and has a loop shape.A
When the u(At) wire 4 is bent as shown by the dotted line (7') in FIG.

本発明は上記のような問題音なく丁ためになされたもの
であって、フレーム倒れ等によるワイヤ曲りやワイヤタ
ッチ等による製品不良の防止を目的とする。The present invention has been made to eliminate the above-mentioned problems and noises, and aims to prevent product defects due to wire bending or wire touching due to frame collapse, etc.

以下実施例にそって本発明を詳述する。The present invention will be described in detail below with reference to Examples.

第４図及び第５図は本発明によるリードフレー　ムを用
いた樹脂封止トランジスタの組立時の一実施形態を示す
。同図に示すようにタブ２上にぺ１ノツト（半導体素子
）１を取り付け、ペレットとボストリード４．５との開
業ワイヤ７でループ接続した状態でボストリード４．５
にワイヤループ７の高さｂよりも高い突起部１１．．１
．２′に上記ワイヤループを囲むように設けｔものであ
る。FIGS. 4 and 5 show an embodiment of the assembly of a resin-sealed transistor using a lead frame according to the present invention. As shown in the figure, a pellet (semiconductor element) 1 is mounted on the tab 2, and the boss lead 4.5 is connected in a loop with the opening wire 7 between the pellet and the boss lead 4.5.
The protrusion 11. is higher than the height b of the wire loop 7. ．． 1
．． 2' is provided so as to surround the wire loop.

例えばタブ上面よりのベレットの高さａは約３００　ｐ
　ｍ　、　　ワイヤループの高さくｈ）は１．０００　
ｐｍ程度であり、ボストリードの突起部１１．１２の高
さｃ　ｆ　１〜２間に形成することにより、このリード
フレームがベレット側音下にして倒れた場合も上記突起
部１１．１２によって保護されワイヤ曲りやワイヤタッ
チ全防止することができる。For example, the height a of the bellet from the top of the tab is approximately 300 p.
m, wire loop height h) is 1.000
pm, and by forming the protrusion 11.12 of the boss lead between the height c f 1 and 2, even if this lead frame falls under the bellet side, it will be protected by the protrusion 11.12. Wire bending and wire touching can be completely prevented.

ボストリードの突起部１１，１２１／ｉ例えば第５図に
示すようにボストリード４，５の先端の一部ｋ　ＩＪ−
ド面に直角に折り曲げることによって形成することがで
きる。上記突起部１１．１２は樹脂モールド後における
リード（ゆるみやり一ド抜ｔＪヲ防＋ｈすることができ
る。Projections 11, 121/i of boss leads 11, 121/i For example, as shown in FIG.
It can be formed by bending at right angles to the surface. The protrusions 11 and 12 can prevent the leads from becoming loose or being pulled out after resin molding.

このような突起部は必しもボストリードに酸レノるとは
限らなり。一つのリードフレームには通當１５〜３０個
のトランジスタのためのリードが例えば第６図に示すよ
うに配列’Ｊ　７１．でいる。そこでこれら榎数の組の
トランジスタ全組立てるループワイヤケ全てカバーする
ように、フレームの周囲部に突起部１３全形成すること
によって個々のトランジスタのループワイヤを保護する
のと同じ効呆全も之せることができる。突起部を形成し
たリードフレームは樹脂モールド後に本体部分から切り
離されることになる。Such protrusions do not necessarily lead to acid leaks on the boss lead. One lead frame has leads for approximately 15 to 30 transistors arranged in an array 'J71.' as shown in FIG. 6, for example. I'm here. Therefore, it is possible to achieve the same effect as protecting the loop wires of individual transistors by forming the entire protrusion 13 around the frame so as to cover all the loop wires for assembling all of the transistors in these pairs. can. The lead frame with the protrusion formed thereon is separated from the main body portion after resin molding.

こｎまでの説明では樹脂刺止トランジスタ全例としたが
、本発明は樹脂封＋、ｆ：１０（＋導体集積回路）［つ
いても同様に応用できる１、第７図ｔよＸａ用の多斂の
リードを具えたリードフレームに本発明全適用した場合
の例全示す。この場合一つの長連のフレームに複数組の
ＩＣに対応するり−ド群が配列さｎたリードフレームが
使用されるがワイヤループを保護するための突起はフレ
ームの側面の一部１４を突当てせてこれを直角に折り曲
けることにより形成することができる。In the explanation so far, all examples of resin-sealed transistors have been described, but the present invention can be similarly applied to resin-sealed +, f: 10 (+ conductor integrated circuit) [1, An example in which the present invention is fully applied to a lead frame equipped with a square lead will be shown. In this case, a lead frame is used in which wire groups corresponding to multiple sets of ICs are arranged in one long frame, but the protrusions for protecting the wire loops protrude from part 14 of the side surface of the frame. It can be formed by bending it at right angles.

以上、実施例で述べた本発明によ扛ば、リードフレーム
においてワイヤループを囲むように突起を設け、その高
さがワイヤループ以上の高さであｎばフレーム倒ｎやフ
レームの治具等への接触によってもワイヤが保護され、
ワイヤ曲りやワイヤタッチ不良會大幅に低減できる効果
奮有する。竹にワイヤタッチがあるかどうかは目視等に
よっても発見が難しく、したがって本発明によれば不良
品の低減に寄与するところ大である。As described above, according to the present invention described in the embodiments, a protrusion is provided in the lead frame so as to surround the wire loop, and if the height of the protrusion is higher than the wire loop, the frame can be tilted or the frame jig can be used. The wire is also protected by contact with
It is highly effective in significantly reducing wire bending and wire touch defects. It is difficult to detect whether there is wire touch in bamboo by visual inspection or the like, so the present invention greatly contributes to reducing the number of defective products.

本発明は大型から小型１での樹脂封止型トランジスタ、
樹脂封止型工Ｃの全てに適用できる。The present invention provides resin-sealed transistors ranging from large to small size 1.
It can be applied to all resin sealing molds C.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のリードフレームのペレット取り付は時の
例を示す平面図、 第２図は同じくその一部正面断面図である。 第３図はリードフレーム全治具上に立てがりる状態７示
す一部断面側面図である。 第４図は本発明によるリードフ＋／、７ｂのぺＬノット
取付は時のｆ１？ｒ−示す一部止面１＠「面図、第５図
は同じく一部斜面図である。 第６図及び第７図は本発明によるリ−ドフ１／−ムのペ
レット取付は時の（（ｔｌの例全示す斜面図である。 １・・・ベレット（素子）、２・・・タブ、３・・・タ
ブリ−４”、、４．５・・・ボストリード、６・・・フ
レーノ・、７・・・ワイヤ、８・・・樹脂モールド体、
９・・・溝、】０・・・治具、１１．　、１．２　、１
３　、１４・・・突起部。 第　　１　　図 第　　２　　図 第　　３　　図 Ａｌ１図 第　　５　　図FIG. 1 is a plan view showing an example of a conventional lead frame with pellets attached, and FIG. 2 is a partially front sectional view thereof. FIG. 3 is a partially sectional side view showing a state 7 in which the lead frame stands up on the whole jig. Fig. 4 shows the installation of the leadoff +/7b PEL knot according to the present invention at f1? Fig. 5 is a partially oblique view. Figs. (It is a slope view showing all examples of tl. 1...Bellet (element), 2...Tab, 3...Tabry-4'', 4.5...Bost reed, 6...Freno... , 7... wire, 8... resin molded body,
9...Groove, ]0...Jig, 11. , 1.2 , 1
3, 14... protrusion. Figure 1 Figure 2 Figure 3 Figure Al1 Figure 5

Claims (1)

【特許請求の範囲】[Claims] １　半導体素子を取り付けるためのタブケイ１するリー
ドと、それ以外のボストリードとをフレーム部と一体に
形成したリードフレームにおいて、タブに半導体素子を
取り付け、素子とボストリードの間を金属ワイヤループ
で接続した状態でワイヤルーズの高場より高い突起部を
このワイヤループを囲むボス）　ＩＪ−ド又はフレーム
の一部に設けｔこと’に％徴とする半導体装置用リード
フレーム。1 In a lead frame in which a tab lead for attaching a semiconductor element and other boss leads are integrally formed with the frame part, a semiconductor element is attached to the tab, and a metal wire loop is connected between the element and the boss lead. A lead frame for a semiconductor device in which a protrusion higher than the height of a loose wire is provided on a part of the IJ-do or frame (a boss surrounding the wire loop).
JP57156649A 1982-09-10 1982-09-10 Lead frame for semiconductor device Pending JPS5947748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57156649A JPS5947748A (en) 1982-09-10 1982-09-10 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57156649A JPS5947748A (en) 1982-09-10 1982-09-10 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5947748A true JPS5947748A (en) 1984-03-17

Family

ID=15632269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57156649A Pending JPS5947748A (en) 1982-09-10 1982-09-10 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5947748A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2584862A1 (en) * 1985-07-12 1987-01-16 Eurotechnique Sa PROCESS FOR THE CONTINUOUS PRODUCTION OF MICROMODULES FOR CARDS CONTAINING COMPONENTS, CONTINUOUS STRIP OF MICROMODULES AND MICROMODULES PRODUCED BY SUCH A METHOD
JPH01109755A (en) * 1987-10-22 1989-04-26 Nec Corp Lead frame
EP0785575A3 (en) * 1996-01-17 1998-09-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and semiconductor module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2584862A1 (en) * 1985-07-12 1987-01-16 Eurotechnique Sa PROCESS FOR THE CONTINUOUS PRODUCTION OF MICROMODULES FOR CARDS CONTAINING COMPONENTS, CONTINUOUS STRIP OF MICROMODULES AND MICROMODULES PRODUCED BY SUCH A METHOD
JPH01109755A (en) * 1987-10-22 1989-04-26 Nec Corp Lead frame
EP0785575A3 (en) * 1996-01-17 1998-09-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and semiconductor module

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