KR0156335B1 - A semiconductor chip package using a tie bar - Google Patents
A semiconductor chip package using a tie bar Download PDFInfo
- Publication number
- KR0156335B1 KR0156335B1 KR1019950033330A KR19950033330A KR0156335B1 KR 0156335 B1 KR0156335 B1 KR 0156335B1 KR 1019950033330 A KR1019950033330 A KR 1019950033330A KR 19950033330 A KR19950033330 A KR 19950033330A KR 0156335 B1 KR0156335 B1 KR 0156335B1
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- tie bar
- die pad
- chip package
- package
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000465 moulding Methods 0.000 claims abstract description 8
- 239000004593 Epoxy Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 2
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 발명은 칩을 안착시킨 다이 패드를 고정하기 위한 타이 바에 관한 것으로서, 더욱 상세하게는 다이패드를 고정하는 타이 바에 다수의 내부 리이드를 동시에 고정할 수 있도록 하기 위한 타이 바를 이용한 반도체 칩 패키지에 관한 것이다.The present invention relates to a tie bar for fixing a die pad on which a chip is seated, and more particularly, to a semiconductor chip package using a tie bar for simultaneously fixing a plurality of internal leads to a tie bar for fixing a die pad. .
본 발명은, 다이패드, 칩, 리이드 및 와이어로 구성한 반도체 칩을 에폭시로 몰딩하여 성형한 반도체 칩 패키지에 있어서, 상기 다이패드와 내부리이드를 그 하부에서 고정하기 위한 타이 바로 구성함을 특징으로 하는 타이 바를 이용한 반도체 칩 패키지이다.The present invention is a semiconductor chip package formed by molding a semiconductor chip consisting of a die pad, a chip, a lead and a wire with epoxy, wherein the tie bar for fixing the die pad and the inner lead is formed thereon. It is a semiconductor chip package using tie bars.
이상에서와 같은 본 발명의 작용과 효과를 살펴보면 다음과 같다.Looking at the operation and effects of the present invention as described above are as follows.
박형 패키지용 리드 프레임의 두께가 얇아짐에 따른 변형가능성의 증가를 방지하는 작용이 가능하며 조립공정중에 리드 프레임의 변형 가능성을 억제할 수 있음과 동시에 단번에 타이 바를 설치함으로써 다이 패드의 변성에 의한 와이어의 파손을 방지하여 반도체 칩 패키지의 신뢰성을 향상 시킬 수 있는 효과가 있다.It is possible to prevent the increase of the deformability as the thickness of the lead frame for the thin package becomes thin. It is possible to suppress the deformability of the lead frame during the assembling process. By preventing the breakage of the semiconductor chip package it is possible to improve the reliability of the package.
Description
제1도는 종래의 반도체 칩 패키지를 나타내는 단면도.1 is a cross-sectional view showing a conventional semiconductor chip package.
제2도는 본 발명의 타이 바를 이용한 반도체 칩 패키지를 나타내는 단면도.2 is a cross-sectional view showing a semiconductor chip package using a tie bar of the present invention.
제3도는 (a)는 본 발명의 타이 바를 나타내는 평면도.3 is a plan view showing a tie bar of the present invention.
(b)는 본 발명의 타이 바를 이용한 반도체 칩 패키지를 나타내는 평면도.(b) is a top view which shows the semiconductor chip package using the tie bar of this invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 다이패드 12 : 칩10: die pad 12: chip
14 : 타이 바 16 : 리이드14: tie bar 16: lead
18 : 와이어 20 : 에폭시 몰딩18: wire 20: epoxy molding
22 : 내부 리이드 24 : 단방향바22: inner lead 24: unidirectional bar
26 : 장방향바26: long direction bar
본 발명은 칩을 안착시킨 다이 패드를 고정하기 위한 타이 바에 관한 것으로서, 더욱 상세하게는 다이패드를 고정하는 타이 바에 다수의 내부 리이드를 동시에 고정할 수 있도록 하기 위한 타이 바를 이용한 반도체 칩 패키지에 관한 것이다.The present invention relates to a tie bar for fixing a die pad on which a chip is seated, and more particularly, to a semiconductor chip package using a tie bar for simultaneously fixing a plurality of internal leads to a tie bar for fixing a die pad. .
일반적으로 반도체 칩 패키지는 고정의 회로가 집적되어 있는 반도체 칩과, 그 반도체 칩이 탑재되는 다이패드와, 그 반도체 칩의 본딩패드들을 외부회로와 연결하기 위해 그 본딩패드에 본딩와이어에 의해 전기적으로 각각 연결되는 리이드들과, 그 반도체 칩과 다이패드 및 리이드들의 내부리이드들을 에워싸는 패키지 몸체로 구성된다. 이러한 반도체 칩 패키지는 인쇄회로기판에 실장되는 형태에 따라 표면 실장형(surface mounted)이나 삽입형(insert)으로 구분된다.Generally, a semiconductor chip package includes a semiconductor chip in which fixed circuits are integrated, a die pad on which the semiconductor chip is mounted, and a bonding wire on the bonding pad to connect the bonding pads of the semiconductor chip with an external circuit. It consists of leads that are connected to each other, and a package body that surrounds the semiconductor chip, the die pad and the inner leads of the leads. The semiconductor chip package is classified into a surface mounted type or an insert type according to a form mounted on a printed circuit board.
최근의 반도체 산업에 있어서, 반도체 소자를 외부 환경으로부터 보호하고 외부단자와의 용이한 연결 및 반도체에 소자의 동작에 대한 신뢰성을 확보하기 위해 에폭시계 성형수지(EMC:Epoxy Molding Compound)를 사용하여 봉지된 플라스틱 패키지가 주로 사용되고 있다.In the recent semiconductor industry, encapsulation is performed using epoxy molding compound (EMC) to protect semiconductor devices from the external environment, to facilitate connection with external terminals, and to ensure reliability of device operation in semiconductors. Plastic packages are mainly used.
일반적인 플라스틱 패키지는 사각형상의 다이패드상에 반도체 칩이 실장되고, 상기 다이패드의 주변에 소정의 간격으로 이격되어 있으며 일정 간격으로 배열되어 있는 리이드들의 일측과 상기 반도체 칩의 상면에 형성되어 있는 본딩패드들이 와이어로 연결되며, 상기 다이패드, 반도체 칩, 본딩 와이어, 내부리이드들은 에폭시계 성형수지로 봉지되며(성형된 에폭시계 성형 수지 부분은 패키지 몸체라 함)상기 패키지 몸체의 외부로 돌출되어 있는 외부리이드들이 실장에 적합한 형상으로 절곡됨으로써 완성된다.In a general plastic package, a semiconductor chip is mounted on a rectangular die pad, and a bonding pad is formed on one side of leads arranged at regular intervals and spaced at predetermined intervals around the die pad and on an upper surface of the semiconductor chip. The die pad, the semiconductor chip, the bonding wire, and the inner leads are encapsulated with an epoxy-based molding resin (the molded epoxy-based resin part is called a package body). The leads are completed by bending them into a shape suitable for mounting.
제1도는 종래의 반도체 칩 패키지를 나타내는 단면도이다.1 is a cross-sectional view showing a conventional semiconductor chip package.
먼저, 다이패드(10)의 상부에 칩(12)을 부착시키고 상기 다이 패드(10)와 일정간격 떨어진 위치에 리이드(16)를 위치시킨 후 상기 칩(12)과 리이드(16)를 와이어(18)로 연결시킨다.First, the chip 12 is attached to the upper portion of the die pad 10, and the lead 16 is positioned at a position spaced apart from the die pad 10 by a predetermined distance. Then, the chip 12 and the lead 16 may be wired. 18).
이때, 전술한 바와 같이 구성된 반도체 칩은 외부의 약한 충격에도 쉽게 손상을 받으며 수분의 침투가 가능하기 때문에 상기 반도체 칩의 보호를 위하여 에폭시 수지로 몰딩하게 된다.At this time, the semiconductor chip configured as described above is easily damaged even by a weak external shock and can be penetrated with an epoxy resin to protect the semiconductor chip because it can penetrate moisture.
그러나 상기와 같이 에폭시 수지로 몰딩하여 성형하게 될 때 상기 성형과정중에 리이드(16)와 다이패드(10)가 서로 변형을 발생하여 반도체 칩 패키지의 신뢰성을 저하시키는 문제점이 있었다.However, when molding and molding with an epoxy resin as described above, the lead 16 and the die pad 10 are deformed to each other during the molding process, thereby lowering the reliability of the semiconductor chip package.
또한, 반도체 칩 패키지의 신뢰성은 내부 리이드의 길이가 긴 경우에 상기 내부 리이드의 와이어 본딩 공정시의 와이어를 열압착 시킬 때 와이어가 손상되는 문제점이 있었다.In addition, the reliability of the semiconductor chip package has a problem that the wire is damaged when thermocompression bonding the wire during the wire bonding process of the inner lead when the length of the inner lead is long.
그러므로 상기의 문제점을 방지하기 위하여 지지대가 필요하며 상기 지지대는 반도체 칩 패키지의 동작에 영향을 미치지 않는 것이어야 한다.Therefore, in order to prevent the above problem, a support is required and the support must be one that does not affect the operation of the semiconductor chip package.
따라서, 전술한 바와같은 지지대로는 수지로 형성한 타이 바를 사용한다.Therefore, the tie bar formed from resin is used for the support stand as mentioned above.
본 발명은 상기의 문제점을 감안하여 안출한 것으로서, 다이패드와 내부 리이드간의 변형과 와이어의 손상을 방지하기 위해 타이 바를 이용한 반도체 칩 패키지를 제공하는 것을 그 목적으로 한다.The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor chip package using a tie bar to prevent deformation between the die pad and the inner lead and damage to the wire.
상기의 목적을 달성하기 위한 본 발명은, 다이패드, 칩, 리이드 및 와이어로 구성한 반도체 칩을 에폭시로 몰딩하여 성형한 반도체 칩 패키지에 있어서, 상기 다이패드와 내부리이드를 그 하부에서 고정하기 위한 타이 바로 구성함을 특징으로 하는 타이 바를 이용한 반도체 칩 패키지이다.The present invention for achieving the above object, in the semiconductor chip package formed by molding a semiconductor chip consisting of a die pad, a chip, a lead and a wire with epoxy, a tie for fixing the die pad and the inner lead in the lower portion It is a semiconductor chip package using a tie bar characterized by the configuration.
이하, 첨부된 도면을 참조하여 본 발명을 보다 상세하게 설명하면 다음과 같다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제2도는 본 발명의 타이 바를 이용한 반도체 칩 패키지를 나타내는 단면도로서, 먼저, 다이패드(10)의 상부에 칩(12)을 부착 고정시키고 다이패드(10)의 양측으로는 다수의 리이드(16)를 위치시킨다.2 is a cross-sectional view showing a semiconductor chip package using a tie bar of the present invention. First, the chip 12 is attached and fixed to an upper portion of the die pad 10, and a plurality of leads 16 are provided on both sides of the die pad 10. Locate it.
이때, 상기 칩(12)과 리이드(16)를 와이어(18)로 연결하고 다이패드(10)의 하부와 상기 리이드(16)의 하부에 타이 바(14)를 맞대어 고정시킨다.At this time, the chip 12 and the lead 16 are connected by a wire 18, and the tie bars 14 are fixed to the lower part of the die pad 10 and the lower part of the lead 16.
상기 타이 바(14)는 수지를 이용하여 성형한 것이다.The tie bar 14 is molded using a resin.
제3도(a)는 본 발명의 타이 바를 나타내는 평면도이고, (b)는 본 발명의 타이 바를 이용한 반도체 칩 패키지를 나타내는 평면도이다.3A is a plan view showing a tie bar of the present invention, and (b) is a plan view showing a semiconductor chip package using the tie bar of the present invention.
장방향바(26)의 중간부에 각각의 내부 리이드와 대응 가능하도록 다수의 단방향바(24)를 형성하여 타이 바(14)를 형성한 후 상기 타이 바(14)의 상부에 다이 패드(10)를 올려서 고정시키고 상기 다이 패드(10)의 상부에는 칩(12)을 안착 고정한다.After forming the tie bars 14 by forming a plurality of unidirectional bars 24 to correspond to the respective inner leads in the middle of the long bar 26, the die pad 10 on the top of the tie bars 14; ) To raise and fix the chip 12 on the die pad 10.
이때, 타이 바(14)에 형성된 다수의 단방향바(24)는 다이 패드(10)보다 길게 형성되어 각각의 내부 리드(22)가 연결 고정된다.At this time, the plurality of unidirectional bars 24 formed in the tie bar 14 is formed longer than the die pad 10 so that each of the inner leads 22 is fixed.
이상에서와 같은 본 발명의 작용과 효과를 살펴보면 다음과 같다.Looking at the operation and effects of the present invention as described above are as follows.
박형 패키지용 리드 프레임의 두께가 얇아짐에 따른 변형가능성의 증가를 방지하는 작용이 가능하며 조립공정중에 리드 프레임의 변형 가능성을 억제할 수 있음과 동시에 단번에 타이 바를 설치함으로써 다이 패드의 변형에 의한 와이어의 파손을 방지하여 반도체 칩 패키지의 신뢰성을 향상 시킬 수 있는 효과가 있다.It is possible to prevent the increase of the deformability as the thickness of the lead frame for the thin package becomes thin, and to prevent the deformability of the lead frame during the assembling process. By preventing the breakage of the semiconductor chip package it is possible to improve the reliability of the package.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950033330A KR0156335B1 (en) | 1995-09-30 | 1995-09-30 | A semiconductor chip package using a tie bar |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950033330A KR0156335B1 (en) | 1995-09-30 | 1995-09-30 | A semiconductor chip package using a tie bar |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970018283A KR970018283A (en) | 1997-04-30 |
| KR0156335B1 true KR0156335B1 (en) | 1998-12-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950033330A KR0156335B1 (en) | 1995-09-30 | 1995-09-30 | A semiconductor chip package using a tie bar |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0156335B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170002912A (en) | 2015-06-30 | 2017-01-09 | 조인형 | Pipe pliers for multi-purpose |
-
1995
- 1995-09-30 KR KR1019950033330A patent/KR0156335B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970018283A (en) | 1997-04-30 |
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