JPS5967659A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5967659A
JPS5967659A JP17766682A JP17766682A JPS5967659A JP S5967659 A JPS5967659 A JP S5967659A JP 17766682 A JP17766682 A JP 17766682A JP 17766682 A JP17766682 A JP 17766682A JP S5967659 A JPS5967659 A JP S5967659A
Authority
JP
Japan
Prior art keywords
package body
leads
semiconductor device
slope
pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17766682A
Other languages
Japanese (ja)
Inventor
Akira Suzuki
明 鈴木
Yoshiaki Wakashima
若島　喜昭
Kazuhiro Terada
和弘 寺田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17766682A priority Critical patent/JPS5967659A/en
Publication of JPS5967659A publication Critical patent/JPS5967659A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent cracks or breaks of a package body by gradually decreasing the inclination of the side surface of the package body from the neighborhood of leads to the upper and lower directions. CONSTITUTION:A semiconductor pellet 13 is fixed on a tab 12 of a lead frame 10, and the pellet 13 is electrically connected to the leads 11 by wires 14. Next, these are sealed with the package body 15 by resin mold. The inclination of the side surface of the package body 15 is so constituted as to gradually decreases from the neighborhood of the leads 11 to the upper and lower directions. This constitution facilitates release from a mold die; therefore the generation of cracks or breaks in the package body can be prevented.

Description

【発明の詳細な説明】 本発明は半導体装置に関し、特にレジンモールｊ′ ドハッケージ型半導体装置に関するものである、一般に
デュアルインライン型の半導体装置やこれに類似するパ
ッケージ構造の半導体装置では、第１図に示すようにリ
ード１基部間距離ｅ、とパッケージ本体２幅寸法Ｅ等の
外形寸法が規定されている、例えばメモリ等１６ビン用
の半導体装置ではｅ＋　＝７．６２　（３００ｍ１ｌ　
）　、Ｅ＝６．３が一般的である、しかしながら、メモ
リ容量の増大に伴なって封止する半導体素子ペレットの
寸法が大きくなると、パンケージにおける耐湿性等の信
頼性を確保する上からもこれに伴なってパッケージ本体
２の幅寸法Ｅを大きくする必要がある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular to a resin molded package type semiconductor device. For example, in a semiconductor device for 16 bins such as a memory, the external dimensions such as the distance e between the bases of the leads 1 and the width dimension E of the package body 2 are specified as shown in the figure, e+ = 7.62 (300 ml
), E=6.3 is common. However, as the size of the semiconductor element pellet to be sealed increases with the increase in memory capacity, this value is also required to ensure reliability such as moisture resistance in the pan cage. Accordingly, it is necessary to increase the width dimension E of the package body 2.

ところが、リード１間距離ｅ１の方は、実装基板との関
係上これを変更することができない状態にあり、したが
って必然的に第２図に示すようにパッケージ本体２がリ
ードｌの幅一杯に広げられたパッケージ構造が採用され
ることになる、このため、レジンモールドにてパンケー
ジ本体２を形成した半導体装置にあっては、レジンモー
ルド後にリードｌを真直状態から図示のように折曲成形
する際に、パッケージ本体２０幅方向両端部３゜３に曲
げ応力が作用し易く、この曲げ応力によってパンケージ
本体２０両端部３，３にクラックや欠けが発生し、半導
体装置の外観低下を生ずると共に信頼性や強度の低下を
生ずるという問題がある。However, the distance e1 between the leads 1 cannot be changed due to the relationship with the mounting board, so it is inevitable that the package body 2 will be extended to the full width of the leads l as shown in FIG. Therefore, in semiconductor devices in which the pancage body 2 is formed by resin molding, when bending the leads l from a straight state as shown in the figure after resin molding, In addition, bending stress tends to act on both ends 3° 3 in the width direction of the package body 20, and this bending stress causes cracks and chips to occur at both ends 3, 3 of the pan cage body 20, deteriorating the appearance of the semiconductor device and reducing reliability. There is a problem that this causes a decrease in strength.

このような問題に対しては、同図に鎖線で示すように・
パッケージ本体２両端部３，３の側面勾配０゜を９０°
ないしこれに近い値としてリードｌに接する両端部３，
３の肉厚を大きくして強度の増大を図ることが考えられ
るが、勾配を増大することはそれだけレジンモールド時
におけるモールド用金型との抜き勾配が零に近くなるこ
とであり、今度は離型不良を生じてこれによるクラック
の発生およびペレットとレジン界面の引き剥しによる耐
湿性の問題が生じることになる、 したがって本発明の目的は、リード成形によっても不具
合を生じることのない高強度に構成する一方で、モール
ド用金型からの離型を容易に行なって離型における問題
も生じることがなく、これにより信頼性１強度の向上を
図ることができる半導体装置を提供することにある。To solve this problem, as shown by the chain line in the figure,
The side slope of both ends 3, 3 of the package body 2 is 0° to 90°
Or as a value close to this, both ends 3 in contact with the lead l,
It is possible to increase the strength by increasing the wall thickness of 3, but increasing the slope means that the draft angle with the molding die during resin molding becomes close to zero, and this time, the separation This can lead to mold defects, resulting in cracks, and moisture resistance problems due to peeling of the pellet and resin interface.Therefore, the object of the present invention is to create a mold with a high strength structure that will not cause defects even during lead molding. On the other hand, it is an object of the present invention to provide a semiconductor device which can be easily released from a molding die without causing problems in releasing the semiconductor device, thereby improving reliability and strength.

この目的を達成するために本発明はパッケージ本体の両
端部の側面勾配をリード近傍から上下方向に向けて漸減
するようにしている。In order to achieve this object, the present invention is configured such that the side slopes at both ends of the package body gradually decrease in the vertical direction from the vicinity of the leads.

以下、本発明を図示の実施例により説明する。Hereinafter, the present invention will be explained with reference to illustrated embodiments.

第３図は本発明の一実施例を示しており、１０は平板状
に形成し、後工程のパッケージ完了後にリード１１を折
曲成形するリードフレーム、１３はこのリードフレーム
ＩＯのタブ１２に固着した半導体素子ペレットであり、
このペレット１３と前記り一ド１１とをワイヤ１４にて
電気的に接続している。１５はこれらペレット１３．ワ
イヤ１４゜リード１１のインナ部を一体的に封止するパ
ッケージ本体であり、レジン材を所謂トランスファモー
ルド法によって所定形状のモールド用金型内に充填し、
かつこれから離型して外形状を形成している。なお、前
記リード１１の基部間距離Ｃ９は所定の寸法に規定され
ている、 前記パンケージ本体１５は、第４図に一方の端部１６を
拡大図示するように、両端部１６．１６はり一ド１１の
折曲成形箇所近傍に位置してパッケージ本体１５の幅寸
法Ｅ、を増大する一方、両端部１６．１６の各側面は勾
配の異なる２つの面１７．１８にて構成している。即ち
、リード１１に近接する部位の側面１７はその勾配θ、
を９０゜に近い大きなものとし、この側面１７の上また
は下の側面１８の勾配θ２をこれよりも小さなものに構
成しているのである。FIG. 3 shows an embodiment of the present invention, in which 10 is a lead frame formed into a flat plate shape and on which the leads 11 are bent and formed after the packaging is completed in the post-process, and 13 is fixed to the tab 12 of this lead frame IO. It is a semiconductor element pellet made of
The pellet 13 and the lead 11 are electrically connected by a wire 14. 15 are these pellets 13. It is a package body that integrally seals the inner part of the wire 14° lead 11, and a resin material is filled into a molding die of a predetermined shape by the so-called transfer molding method.
The mold is then released to form an external shape. Note that the distance C9 between the bases of the leads 11 is defined as a predetermined dimension.The pancage main body 15 has both ends 16. 11, the width dimension E of the package body 15 is increased, and each side surface of both end portions 16.16 is constituted by two surfaces 17.18 with different slopes. That is, the side surface 17 of the portion close to the lead 11 has a slope θ,
is made large, close to 90 degrees, and the slope θ2 of the side surface 18 above or below this side surface 17 is configured to be smaller than this.

以上の構成によれば、パッケージ本体１５は側面１７の
勾配を９０°に近い大きなものにしているので両端部１
６．１６におけるリード１１近傍の肉厚が大きくなりそ
の強度が増大される。したがって、パッケージ本体１５
の完成後にリードを折曲成形してその曲げ応力がパッケ
ージ本体１５に作用しても両端部１６．１６においてク
リックや欠けが生ずることはない。一方、パッケージ本
体１５は側面１８において勾配が小さくされているため
に、モールド用金型の抜き勾配が小さくなって離型な極
めて容易に行なうことができ、ベレットとレジン界面の
引き剥しか生じることもない、この結果、パッケージ本
体の外観を良好に保持すると共に、クラックや欠は等に
よる耐湿性の低下を防止し、半導体装置の信頼性や強度
の向上を図ることができる、 第５図は本発明の他の実施例を示しており、特にその外
形をのみ図示している。本実施例ではパンケージ本体１
５　Ａの両端部１．６　、　ｌ　６の各側面の勾配を側
面１９，２０．２１とで三段階に異なる勾配θ８．θ４
　、θ、に形成したものである、勿論勾配はθ３〉θ４
〉θ、の関係にしている。According to the above configuration, since the package main body 15 has a large slope of the side surface 17 close to 90 degrees, both ends 1
The thickness near the lead 11 in 6.16 is increased, and its strength is increased. Therefore, the package body 15
Even if the leads are bent and formed and the bending stress is applied to the package body 15 after completion of the package, no clicks or chips will occur at both ends 16 and 16. On the other hand, since the package body 15 has a small slope at the side surface 18, the draft angle of the molding die is small, making it extremely easy to release the mold, and only peeling off the pellet and resin interface occurs. As a result, it is possible to maintain the appearance of the package body well, prevent deterioration of moisture resistance due to cracks and chips, and improve the reliability and strength of the semiconductor device. Another embodiment of the present invention is shown, and in particular, only the outer shape thereof is illustrated. In this embodiment, the pan cage body 1
The slopes of the side surfaces of both ends 1.6 and 16 of 5 A are different in three steps from the slopes θ8. θ4
, θ, and of course the slope is θ3>θ4
The relationship is 〉θ.

このように構成すれば、前記と同様にリード１１近傍の
パッケージ本体１５Ａの肉厚を増大して強度の向上を達
成できる一方で、パンケージ本体の上又は下の勾配を小
さくしてモールド用金型からの離型を更に容易なものに
できる。With this configuration, the thickness of the package body 15A near the leads 11 can be increased in the same way as described above to improve the strength, while the slope of the top or bottom of the pan cage body can be reduced and the molding die can be improved. Release from the mold can be made easier.

なお、本例では勾配を三段階としているので、パッケー
ジ本体の厚さ方向中間部の肉量な前例のものよりも増大
できる一方で、最上又は最下の勾配を更に小さなものに
できる、 ここで、勾配の変化段数を四段以上にしてもよく、更に
は第６図に示すように勾配を連続的に変化してパッケー
ジ本体１５Ｂの側面を曲面状に形成するようにしてもよ
い。In addition, in this example, the slope is in three stages, so while the thickness of the middle part in the thickness direction of the package body can be increased compared to the previous example, the slope at the top or bottom can be made smaller. The number of steps in which the slope changes may be four or more, or the slope may be changed continuously to form a curved side surface of the package body 15B as shown in FIG.

以上のように本発明の半導体装置によれば、パッケージ
本体の側面勾配をリード近傍から上下方向に向けて漸減
するように構成しているので、パッケージ本体のリード
近傍の肉量を多くしてリード曲げ応力に対する強度を増
大する一方でモールド用金型からの離型を容易にし、こ
れによりパッケージ本体のクラックや欠けを防止して半
導体装Ｉ４の信頼性や強度を向上することができるとい
う効果を奏する、As described above, according to the semiconductor device of the present invention, since the side slope of the package body is configured to gradually decrease in the vertical direction from the vicinity of the leads, the thickness of the package body near the leads is increased to While increasing the strength against bending stress, it also facilitates release from the mold, thereby preventing cracks and chips in the package body and improving the reliability and strength of the semiconductor device I4. play,

【図面の簡単な説明】[Brief explanation of drawings]

第１図および第２図は従来装置の不具合を説明するため
の側面図、 第３図は本発明の一実施例の全体断面図、第４図は要部
の拡大図、 第５図および第６図は夫々異なる他の実施例の側面図で
ある、 ｌＯ・・・リードフレーム、ｌｌ・・・リード、１３・
・”ベレット、１４・・・ワイヤ、１５．＋５Ａ、１５
Ｂ・・・パッケージ本体、１６・・・両端部、１７〜２
１・・・側面、θ、〜θ、・・・勾配。 第　　１　　図 第　　２　　図 第　　３　　図 第　　４　図 第　　５　　図 ／／ 第６図Figures 1 and 2 are side views for explaining the problems of the conventional device, Figure 3 is an overall sectional view of an embodiment of the present invention, Figure 4 is an enlarged view of the main parts, Figures 5 and 2 are 6 is a side view of other different embodiments, 10...lead frame, 11...lead, 13.
・"Bellet, 14... Wire, 15. +5A, 15
B...Package body, 16...Both ends, 17-2
1... Side, θ, ~θ,... Slope. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 // Figure 6

Claims (1)

【特許請求の範囲】 １、　レジンモールドにてパッケージ本体を形成してな
る半導体装置において、前記パッケージ本体の側面勾配
を厚さ方向中央に設けたリード近傍部位から厚さ方向上
下に向けて漸減するように構成したことを特徴とする半
導体装置。 ２、側面勾配を二段階に形成してなる特許請求の範囲第
１項記載の半導体装置。 ３、側面勾配を三段階ないし無限段階に形成してなる特
許請求の範囲第１項記載の半導体装置。[Claims] 1. In a semiconductor device in which a package body is formed by resin molding, the side slope of the package body is gradually reduced upward and downward in the thickness direction from a region near the leads provided at the center in the thickness direction. A semiconductor device characterized in that it is configured as follows. 2. The semiconductor device according to claim 1, wherein the side slope is formed in two stages. 3. The semiconductor device according to claim 1, wherein the side slope is formed in three to infinite steps.
JP17766682A 1982-10-12 1982-10-12 Semiconductor device Pending JPS5967659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17766682A JPS5967659A (en) 1982-10-12 1982-10-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17766682A JPS5967659A (en) 1982-10-12 1982-10-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5967659A true JPS5967659A (en) 1984-04-17

Family

ID=16034978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17766682A Pending JPS5967659A (en) 1982-10-12 1982-10-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5967659A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419950B1 (en) * 1997-12-30 2004-06-14 앰코 테크놀로지 코리아 주식회사 manufacturing method of ball grid array semiconductor package using a flexible circuit board
EP2136414A1 (en) * 2007-03-26 2009-12-23 Nichia Corporation Light emitting device
JP2018022837A (en) * 2016-08-05 2018-02-08 トヨタ自動車株式会社 Method for manufacturing semiconductor module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419950B1 (en) * 1997-12-30 2004-06-14 앰코 테크놀로지 코리아 주식회사 manufacturing method of ball grid array semiconductor package using a flexible circuit board
EP2136414A1 (en) * 2007-03-26 2009-12-23 Nichia Corporation Light emitting device
EP2136414A4 (en) * 2007-03-26 2011-08-03 Nichia Corp Light emitting device
US8251530B2 (en) 2007-03-26 2012-08-28 Nichia Corporation Light emitting device
JP2018022837A (en) * 2016-08-05 2018-02-08 トヨタ自動車株式会社 Method for manufacturing semiconductor module

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