KR970030726A - Ball Grid Array Package with Lead Frame - Google Patents

Ball Grid Array Package with Lead Frame Download PDF

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Publication number
KR970030726A
KR970030726A KR1019950040426A KR19950040426A KR970030726A KR 970030726 A KR970030726 A KR 970030726A KR 1019950040426 A KR1019950040426 A KR 1019950040426A KR 19950040426 A KR19950040426 A KR 19950040426A KR 970030726 A KR970030726 A KR 970030726A
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South Korea
Prior art keywords
grid array
array package
ball grid
lead frame
ball
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KR1019950040426A
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Korean (ko)
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KR0173930B1 (en
Inventor
김준식
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김광호
삼성전자 주식회사
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Priority to KR1019950040426A priority Critical patent/KR0173930B1/en
Publication of KR970030726A publication Critical patent/KR970030726A/en
Application granted granted Critical
Publication of KR0173930B1 publication Critical patent/KR0173930B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 본딩 패드가 일면에 형성된 반도체 칩과, 복수개의 내부 리드를 가지며 상기 반도체 칩이 안착되는 리드 프레임과, 상기 반도체 칩의 외부로의 전기적 연결을 위한 복수개의 솔더 볼과, 상기 솔더 볼이 노출되도록 함과 동시에 상기 소자들을 감싸 보호하도록 형성된 패키지 몸체를 구비하는 볼 그리드 어레이 패키지에 있어서, 상기 리드 프레임의 내부 리드 영역에 솔더 볼이 안착되어 있으며, 상기 반도체 칩의 본딩 패드가 와이어 본딩에 의해서 상기 내부 리드에 전기적으로 연결된 볼 그리드 어레이 패키지를 제공함으로써, 리드 프레임을 사용하여 반도체 제품의 외형을 최소한도로 줄일 수 있어서, 칩 크기의 패키지화 하는 매우 유리하며, 기존 공정을 이용하므로 제작이 매우 쉽고, 리드프레임이 제품외부로 돌출되어 있고, 재질이 금속으로 되어 있어 열방출이 좋으며 플라스틱 성형 수지와의 결합력이 우수하여 패키지의 신뢰성을 확보하는 효과가 있다.According to the present invention, a semiconductor chip having a bonding pad formed on one surface thereof, a lead frame having a plurality of internal leads, and the semiconductor chip is seated thereon, a plurality of solder balls for electrical connection to the outside of the semiconductor chip, and the solder balls In the ball grid array package having a package body formed to expose and protect the elements at the same time, the solder ball is seated in the inner lead region of the lead frame, the bonding pad of the semiconductor chip by the wire bonding By providing a ball grid array package electrically connected to the internal leads, it is possible to reduce the appearance of semiconductor products to a minimum by using a lead frame, which is very advantageous to package the chip size, and is very easy to fabricate using an existing process, Lead frame protrudes out of the product and is made of metal The heat dissipation is good, and the bonding force with the plastic molding resin is excellent, thereby ensuring the reliability of the package.

Description

리드 프레임을 이용한 볼 그리드 어레이 패키지Ball Grid Array Package with Lead Frame

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 2도는 본 발명에 의한 일 실시예에 따른 볼 그리드 에레이 패키지의 구조를 나타낸 단면도.2 is a cross-sectional view showing the structure of a ball grid array package according to an embodiment of the present invention.

제 3도는 본 발명에 따른 볼 그리드 패키지에 사용되는 리드프레임에 반도체 칩이 실장되어 와이어 본딩이 완료된 상태를 나타낸 평면도.3 is a plan view illustrating a state in which wire bonding is completed by mounting a semiconductor chip on a lead frame used in a ball grid package according to the present invention.

제 4a도는 딤플(dimple)이 형성된 솔더 볼 안착부를 나타낸 사시도.Figure 4a is a perspective view showing a solder ball seating dimple formed.

제 4b도는 그루브(groove)가 형성된 솔더 볼 안착부를 나타낸 사시도.4b is a perspective view of a solder ball seat with grooves formed therein;

Claims (8)

본딩 패드가 일면에 형성된 반도체 칩과, 복수개의 내부 리드를 가지며 상기 반도체 칩이 안착되는 리드 프레임과, 상기 반도체 칩의 외부로의 전기적 연결을 위한 복수개의 솔더 볼과, 상기 솔더 볼이 노출되도록 함과 동시에 상기 소자들을 감싸 보호하도록 형성된 패키지 몸체를 구비하는 볼 그리드 어레이 패키지에 있어서, 상기 리드 프레임의 내부 리드 영역에 솔더 볼이 부착되어 있으며, 상기 반도체 칩의 본딩 패드가 와이어 본딩에 의해서 상기 내부 리드에 전기적으로 연결되어 있는 것을 특징으로 하는 리드 프레임을 이용한 볼 그리드 어레이 패키지.A bonding pad having a bonding pad formed on one surface, a lead frame having a plurality of internal leads, and on which the semiconductor chip is seated, a plurality of solder balls for electrical connection to the outside of the semiconductor chip, and the solder balls are exposed. A ball grid array package having a package body formed to surround and protect the devices, wherein a solder ball is attached to an internal lead region of the lead frame, and a bonding pad of the semiconductor chip is connected to the internal lead by wire bonding. Ball grid array package using a lead frame, characterized in that electrically connected to. 제 1항에 있어서, 상기 내부 리드가 솔더 볼의 부착을 위하여 내부 리드의 폭 보다 큰 폭으로 돌출된 솔더 볼 안착부를 갖는 것을 특징으로 하는 리드 프레임을 이용한 볼 그리드 어레이 패키지.The ball grid array package of claim 1, wherein the inner lead has a solder ball seating portion protruding to a width greater than a width of the inner lead for attaching the solder ball. 제 2항에 있어서, 상기 내부 리드의 솔더 볼 안착부가 솔더 볼과의 결합력을 높이기 위하여 딤플(dimple)이 형성된 것을 특징으로 하는 리드 프레임을 이용한 볼 그리드 어레이 패키지.The ball grid array package of claim 2, wherein a dimple is formed in order to increase a bonding force of the solder ball seating portion of the inner lead with the solder ball. 제 2항에 있어서, 상기 내부 리드가 솔더 볼 안착부에 그루브(groove)가 형성되어 있는 것을 특징으로 하는 리드 프레임을 이용한 볼 그리드 어레이 패키지.The ball grid array package according to claim 2, wherein a groove is formed in the solder ball seating portion of the inner lead. 제 1항에 있어서, 상기 내부 리드의 하부 면이 외부로 돌출 되도록 성형수지로 성형되어 있는 것을 특징으로 하는 리드 프레임을 이용한 볼 그리드 어레이 패키지.The ball grid array package according to claim 1, wherein the lower surface of the inner lead is formed of a molding resin so as to protrude outward. 제 1항에 있어서, 상기 솔더 볼이 서로 어긋나게 배열되어 내부 리드 면에 부착되어 있는 것을 특징으로 하는 리드 프레임을 이용한 볼 그리드 어레이 패키지.The ball grid array package according to claim 1, wherein the solder balls are arranged to be offset from each other and attached to an inner lead surface. 제 1항 또는 제 2항에 있어서, 상기 내부 리드들의 솔더 볼 안착부가 서로 어긋나게 배열되도록 형성되어 있는 것을 특징으로 하는 리드 프레임을 이용한 볼 그리드 어레이 패키지.The ball grid array package according to claim 1 or 2, wherein the solder ball seating portions of the inner leads are arranged to be offset from each other. 제 2항에 있어서, 상기 솔더 볼의 크기가 리드에 부착될 수 있는 크기인 것을 특징으로 하는 리드 프레임을 이용한 볼 그리드 어레이 패키지.The ball grid array package of claim 2, wherein the solder ball has a size that can be attached to a lead. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950040426A 1995-11-09 1995-11-09 Ball grid array for lead frame KR0173930B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980039676A (en) * 1996-11-28 1998-08-17 황인길 Easy to mount bottom lead package chip scale package
KR20000035276A (en) * 1998-11-06 2000-06-26 가네코 히사시 BGA type semiconductor device package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980039676A (en) * 1996-11-28 1998-08-17 황인길 Easy to mount bottom lead package chip scale package
KR20000035276A (en) * 1998-11-06 2000-06-26 가네코 히사시 BGA type semiconductor device package

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