JPS594171A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve electric characteristics of a semiconductor device by forming diffused layers of source and drain separately in the first and second diffusing steps, and forming double diffused layers of different diffusion depths and defferent impurity densities. CONSTITUTION:The first gate oxidized film 3, the first polysilicon film 4 to become a floating gate, the second gate oxidized film 5 and the second polysilicon film 6 to become a control gate are formed in the region which is surrounded by an interelement isolating oxidized film 2 of a substrate 1 in a double gate structure, arsenic ions are then implanted from the double gate, a heat treatment is performed in nitrogen atmosphere, thereby obtaining shallow diffused layers 8, 8 to become source and drain. Then, parts of the double gate structure and the part of the layers 8, 8 of the same structure side are covered with a resist pattern 9. With the pattern 9 as a mask, arsenic ions are then implanted, the pattern 9 is then removed by oxygen plasma etching, heat treatment is then performed in nitrogen atmosphere, thereby forming shallow diffused layers 8a, 8a of approx. 0.2mum and diffused layers 8b, 8b which are deeper by 0.45mum than the layers 8a, 8a.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for forming source/drain diffusions in a memory section or a peripheral circuit element section in a nonvolatile semiconductor memory device having a double gate structure. be.

In recent years, in this type of nonvolatile semiconductor memory device,
As the degree of integration increases, a method using arsenic diffusion is commonly used to form source and drain portions of devices. That is, in this conventional method, as shown in FIG.
), a first gate oxide film (3), 70
- A first polysilicon film (4) and a second gate oxide film (5), which will serve as a gate gate.

and a second polysilicon film (
After forming the double gate structure of 6), arsenic is selectively implanted into the substrate (1) from above the double gate by ion implantation, and the diffusion of this arsenic is promoted by heat treatment to form the source/drain structure. A diffusion layer (7) was formed.

However, in this method of forming sources and drains using an arsenic diffusion layer, the diffusion of arsenic in the silicon substrate is slower than in the conventional method of forming sources and drains using a phosphorus diffusion layer. There is a problem in that the concentration distribution changes rapidly between the diffusion layer and the substrate, and the electrical withstand voltage at the source-drain junction decreases.

In view of these conventional drawbacks, this invention improves the electrical characteristics by forming double source/drain diffusion layers with different diffusion depths and arsenic implantation amounts. ＠The following is an example of the method of this invention shown in FIG.

This will be explained in detail with reference to FIG.

First, in the method of the embodiment shown in FIG. 2, as in the conventional method,
A first gate oxide film (3), a first polysilicon film (4) serving as a floating gate, and a second gate oxide film ( 5), and a second polysilicon film (6) which will serve as a control gate, are formed into a double gate structure by photolithography and etching techniques as is well known, and then arsenic ions 5 are injected into the double gate by ion implantation.
0 KeV, I x 10'' theory implantation, and heat treatment for 950'0.30 minutes in a nitrogen atmosphere,
A shallow diffusion layer (8) that will eventually become the source and drain,
(8) is obtained ((a) in the same figure).

Next, a part of the double gate structure and the diffusion layer +8) on the side of the same structure is covered with a resist pattern (9) (FIG. 2(b)), and this resist pattern (9) is covered.
t= mask, and similarly to arsenic ion 50 eV.

After implantation at 4 x 101s/cd, this resist pattern (9) is removed by oxygen plasma etching, and heat treatment is performed for 1000mm for 0.30 minutes in a nitrogen atmosphere to form a shallow trench of about 0.2μm. Diffusion layer part (8a
), (8a), and deeper diffusion layer parts (sb) and (sb) of about 0.45P were formed ((C) in the same figure).
.

When 64-FAMO8 was manufactured using the method of the embodiment shown in FIG. 2, the withstand voltage between the source and drain of the memory element with a gate width of 3 μm was 13V in the conventional method, but in this embodiment method, the breakdown voltage between the source and drain was 13V. The same withstand voltage is 20V.
In addition, in the method of the embodiment shown in FIG. 3, after forming the double gate structure, the resist pattern (IG
Using this as a mask, arsenic ions of 50KeV, 4×10” were selectively implanted, and heat treatment was performed at 1000°C for 230 minutes in a nitrogen atmosphere to form the deep diffusion layer portions (8b) and (8b). (a)
Then, after removing the resist pattern 0I by etching, using the double gate structure as a mask, arsenic ions of 50 KeV, I x 10''/7 are implanted by the usual method (Figure (b)), thereby forming the diffusion layer. Part (sb)
, (sb), shallow diffusion layer parts (8a), (8a)
After that, a heat treatment is performed at 950'0° for 30 minutes in a nitrogen atmosphere (FIG. 3(C)). Namely.

This shows that the resist pattern α1 is OF when forming double gates.
Plasma etching according to No. 4 and wet etching using a hydrofluoric acid aqueous solution take advantage of the fact that the etching becomes wider from the edge of the gate, and a double diffusion layer structure similar to that of the embodiment shown in FIG. 2 can be obtained, with similar electrical characteristics. I was able to achieve it.

Although the above embodiments are applied to a memory element portion of a memory device, it goes without saying that the present invention can also be applied to a peripheral circuit element portion in the same way.

As described in detail above, according to the method of the present invention, in manufacturing a nonvolatile memory device with a double gate structure, the diffusion layers that become the sources and drains of the memory element portion or the peripheral circuit element portion are formed in the first diffusion step. and the second diffusion step,
Since it is formed in double diffusion layers having different diffusion depths and impurity concentrations, it has the advantage that the electrical withstand voltage at the source-drain junction can be sufficiently improved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing a conventional method for forming the source and drain of a memory element part in a nonvolatile memory device with a double gate structure, FIGS. 2(a) to (C), and FIGS. 3(a) to 3.
(C) is an explanatory diagram illustrating different embodiments of the memory element source/drain according to the method of the present invention in the order of steps. (1)...Silicon substrate, (2)...Element isolation oxide film, (3), (5)...First. Second gate oxide film (41, (6)...first, second polysilicon film (floating Y gate, control gate), (8)...diffusion layer, (8a), (8b) ...
- Diffusion layer portion, (9)...resist pattern. Agent Shin Kuzuno - (7) Figure 1 Figure 2

Claims (3)

[Claims] (1) In manufacturing a nonvolatile memory device with a double gate structure, impurity diffusion is performed in the first diffusion step and the 1. A method for manufacturing a semiconductor device, which is performed separately in two diffusion steps to form double diffusion layers having different diffusion depths and impurity concentrations. (2) After forming the double gate structure, arsenic ion implantation and heat treatment are performed on the double gate to perform a first diffusion step, then a resist pattern is formed to cover the double gate structure, and the first diffusion step is performed. The semiconductor according to claim 1, wherein a second diffusion step is selectively performed again by arsenic ion implantation and heat treatment on a portion of the diffusion layer obtained in the step except for a portion thereof. Method of manufacturing the device. (3) After forming the double gate structure, arsenic ions are implanted into a selected part of the remaining resist pattern used in the same formation, a first diffusion process is performed by heat treatment, and then the resist is removed. Manufacturing the semiconductor device according to claim 1, wherein the second diffusion step is performed again by arsenic ion implantation and heat treatment on other parts including the diffusion portion obtained in the first diffusion step. Method.