JPS5932154A - Forming method for solder bump - Google Patents

Forming method for solder bump

Info

Publication number
JPS5932154A
JPS5932154A JP57142933A JP14293382A JPS5932154A JP S5932154 A JPS5932154 A JP S5932154A JP 57142933 A JP57142933 A JP 57142933A JP 14293382 A JP14293382 A JP 14293382A JP S5932154 A JPS5932154 A JP S5932154A
Authority
JP
Japan
Prior art keywords
solder
forming
bump
plating
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57142933A
Other languages
Japanese (ja)
Other versions
JPH0226780B2 (en
Inventor
Kenichi Ogawa
健一 小川
Masahiko Kawada
川田　正彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP57142933A priority Critical patent/JPS5932154A/en
Publication of JPS5932154A publication Critical patent/JPS5932154A/en
Publication of JPH0226780B2 publication Critical patent/JPH0226780B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a solder bump simply with plating solution of one type by forming a barrier metal film which is difficult to remove after forming solder in an electrode shape before forming the bump. CONSTITUTION:A protective film 2 is covered except an aluminum electrode 1, Cr, Ni-Cr, Mo or the like is deposited to selectively form the barrier film in an electrode shape. Then, a metal film 4 which is hardly etched at a solder by an etchant for Cu, Ni or Au is superposed thereon, and a bump 6' is formed by solder plating with a positive resist mask which is similarly hardly etched by an exfoliating solution. According to this structure, the bump which has good bondability, high quality in mounting such as bonding strength may be simply obtained.

Description

【発明の詳細な説明】 本発明ｔ、ｊフェースタ゛ウンボンデイ／グなどに使用
されるＶ」−んだバンフセｊ半導体４Ｎ　ｔｄｔ、　ｏ
　Ｉ、ｔんだバング形成力法に関する范のである。[Detailed Description of the Invention] The present invention relates to a V''-type semiconductor 4N semiconductor used for face unbonding and the like.
I. This is a description of the bending bang forming force method.

従来より、めっきＫよるはんだバンズの形成におい１れ
ｊ、％金バンプと異なり、ＩｒＪんだが棹々の薬品に侵
さｈる＋ｌｒ　ｇを有する点から、金バンプの形成方法
のように、パリや皮膜、導電欽属１Ｍ形成後ネ、極以外
の部分にめつきレジス１４−形ｆｉ！ｉ　ｌ〜、Ｖ〕つ
きにて１・、Ｊんだバング形成後、レジスト除去、溝車
金属Ｏｒ、パリや皮膜ヲエッチング除去する方法（第１
図参１１ｊ（）はパリや皮１摸エツチングの際、エツチ
ング液に、Ｆ：りはんだが作され、パンツ形成が出来な
いとい゛）問題が力）つ７ζ。このため、めっきン（−
よるはんだパンツ形ＩＡ：において６・よ、鉛が酷など
の薬品に比仲的強く、エツチング液にも侵されにくい点
ケ利用して、スズめっき、鉛めっきという二層めっきを
行なって、パリや皮膜除去後、熱により二層全合金化す
る方法などが行なわれていたが、こｈらは工程が長くな
る、複雑になるなとの神々の欠点があり、差た二種類の
めつき液、約つき設備が必要になるなど、費用のかさむ
欠点もめった。Conventionally, in the formation of solder buns using K plating, unlike gold bumps, IrJ solder is easily eroded by common chemicals; After forming the film and conductive layer 1M, plate the resist on the part other than the pole 14-type fi! After forming the solder bang with 1. and J with I l ~, V], the resist is removed, and the groove wheel metal Or, paris and film are etched away (first method).
Figure 11j () shows that when etching Paris or leather, F: resolder is formed in the etching solution, making it impossible to form pants. For this reason, plating (−
Solder Pants Type IA: In 6. Taking advantage of the fact that lead is relatively strong against harsh chemicals and is not easily attacked by etching solutions, two-layer plating of tin plating and lead plating is performed. A method of fully alloying two layers using heat after removing the film or coating has been used, but these methods have the disadvantage that the process is long and complicated, and the two different types of plating have been used. It also had the disadvantages of being expensive, such as the need for liquids and equipment.

本発明は上記の工うな欠点を除去し、工程が簡単でかつ
一種のめつき液、めっき設備を使用するはんだバンプの
形成方法を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for forming solder bumps that eliminates the above-mentioned disadvantages, has a simple process, and uses a single plating solution and plating equipment.

本発明のｔ時機とするｎ「は、ｖ」、んだバンプ形成後
には、除去が困φ１ｆ７Ｉパリや皮ｑｇｉバンプ形成前
に電極状に形成し、パンツ形成全行なう点にある。The timing of the present invention is that after the solder bumps are formed, they are difficult to remove, and are formed in an electrode shape before the solder bumps and skin qgi bumps are formed, and the entire pants formation is performed.

以−ト、実施例シ（より本訴、明を詳細に説明する１゜
第２邸１（１）に示す工うに、半導体装置電極相Ｓの断
面は゛アルミ屯イ献とアルミ市柄・外には配線床Ｒム嗅
が形成さノ土ている。これに？−バリや皮ＩＩ＠を電極
状に形清１゛る。（第２図（２））この方法としては、
蒸着。Hereinafter, the cross section of the semiconductor device electrode phase S is as shown in Example 1 (more detailed description of the present lawsuit). The wiring floor Rum is formed in the soil.Then, burrs and skin II@ are shaped into electrodes.(Fig. 2 (2)) This method is as follows.
Vapor deposition.

スパツクなどに、しり全面（化バリーや皮嘆形成後、フ
ォトエッヂングｌム（ｐｉ−より′市（セ状パターン全
形成する方法、Ｗｆ極部は外にレジスト形成１、た荏、
パリや皮ｊｌ／Ｊ　ｆ、全面に形成し、リフトＡ］によ
り゛ｇ１．極状パターン全形成−する方法、メタルマス
クＡ　＞ｔＪ　Ｋ　、ｊ：す、Ｔｉ［ケ状パターンを形
チする方法ｌとが使用される。After the formation of burrs and skin lesions on the entire surface of the buttocks, etc., photo-etching (method of forming the entire square pattern from pi-, resist formation 1 on the outside of the Wf extreme part,
Paris and skin jl/Jf are formed on the entire surface and lifted by [g1. A method for forming the entire polar pattern is used, and a method for forming a metal mask A > tJ K , j: S, Ti [method for forming a square pattern] is used.

パリや皮膜相Ｊミとしてｖ、ｔ、クロＡ　、ニクロム。V, T, Kuro A, Nichrome as Paris and film phase J Mi.

モリブデンなどを使用する。Use molybdenum etc.

次に、クエ・・全面にめっき性の良い導電金属１換を形
成し、さらにめっきレジストとしてフォトレジストによ
り電極部以外をコートする。（第２図（３）） ここで、嗜、′屯幣属１関としては、めつき１生が良く
かつ導ｎｙ金域膜除去の際、そのエツチング液がはんた
を侵しＬ　（い、−・ｌ、ニッケル、＠なとをイ史用す
る。またフォトレジストとしては、レジスト除去の際、
レジストはぐり沿がはんだ金侵し７にくい・１ミジ系レ
ジストを使用′４ることが好オしい。Next, a conductive metal with good plating properties is formed on the entire surface, and then areas other than the electrode portions are coated with photoresist as a plating resist. (Fig. 2 (3)) Here, as a matter of course, when the plating is good and the solder is removed, the etching solution corrodes the solder. , -・l, nickel, and @nato are used for photoresist.When removing the resist,
It is preferable to use a 1-millimeter resist that resists solder metal corrosion along the resist edges.

次に、Ｉｒ１．んだめつき液を使ＩＴコシて車砿部には
んだパンツ勿形成する。（％２図（４））コｒ５しｒｌ
ｌ）合に工って１ｌ−１、ｄんだめつき前に銅、ニッケ
ル々どの尚融点スクーヘバンフを形成した陵、はんたバ
ング゛が形成符ｉする。Next, Ir1. Using solder solution, solder pants are formed on the car's metal parts. (%2 figure (4)) ko r5 and rl
l) A solder band is formed by joining the solder plate to form a solder bump of copper, nickel, etc. before solder plating.

１け伝り（、レジスト除去全イボない、４奄釜慎＋Ｓ金
エツチングしＣ＆まんだバングオ先成させる。（泥２図
（５）） 以上のよう・配して形成されたはんだバングは、バング
形状、強度も問題なく、捷た載（んだが侵されて、バン
グ形成が出来なＩ／−１などの不良もみらＩｔず１品質
上溝足なものであった。(Remove the resist to remove all warts.) 4. Remove the resist + S gold etching and form the C & mand bang. (Fig. 2 (5)) The solder bang formed as described above is There were no problems with the shape or strength of the bang, and there were no defects such as I/-1 where the solder was corroded and the bang could not be formed, and the quality was poor.

また、このはんだバングは、ボンティング性、ボンデ４
フフ強ｎ〔などの実装上の品′べにａ’＞Ｈし）ても１
．４足すべきものであった。In addition, this solder bang has excellent bonding properties and bonding properties.
Fufu strong n
．． It should have been four.

以上述べＣきた上うに・ト・尾明に上れは、工程が１７
ｉ’ｉ単でめっき液、めっき設備も一種類で可能なはん
だバング形成が可能になるものである。。As mentioned above, there are 17 steps in the above process.
It is possible to form solder bangs using only one type of plating solution and one type of plating equipment. .

４、１４１面の簡、Ｍ４な説明 第１図は−バンフーの形成方法、第２図は本発明のはん
たバンプ形成方法の′＊施例を示す工程１打ｒ面図であ
る。4. Simple, M4 description of the 141st surface FIG. 1 is a step-by-step r side view showing a method for forming a solder bump, and FIG.

１・・・・・・アルミ１６．１繭　　　２・・・・・・
院内保護膜３・・・・・・パリや皮膜　　　４・・・・
・・４戦＠唄嗅５・・・・・レジスト　　　　６・・・
・・・ノくンフ以　　　上 出願人　を末代会社　絹二精工舎 代理人　弁理士　最上　　務1... Aluminum 16.1 cocoon 2...
In-hospital protective film 3...Paris and film 4...
・・4th battle @Utano 5・・・Resist 6・・・・
・・・Nokunfu The applicant is the subsidiary company Kinuji Seikosha agent Patent attorney Tsutomu Mogami

Claims (1)

【特許請求の範囲】 半導体装置のアル＜ｍ４徹土へのはんだバンプの形成方
法において、アルミ１ｉ４、極上にクロム、ニクロム、
モリブテンなとのバリヤ皮膜電極を形成する工程、−）
：　Ｈ＋、”ｔｌｌ、榛紮含む半導体クエハ全面に銅、
ニンケル、金ろどのめっき性の良い７ｂ亀金蛎暎を形成
し、電極以外の部分にめっきレジストを形成−ｊ”　ル
工程、−１：　ｍｅ　１（１：　、ｊｉｊｉ　（ｆ３　
Ｋ　メツきＫ　Ｘｆ）Ｉｒ；Ｉ　ＡＪｅ　バンプを形成
する工程、上記の処理を行なったワエハをレジスト除去
後、エツチングに、【り上記導電雀閥膜を除去する１柏
：よりなるｉｔんだパンツの形成ｌｊ法。[Claims] A method for forming solder bumps on aluminum < m4 solid earth of a semiconductor device, wherein aluminum 1i4, chromium, nichrome,
Step of forming a barrier film electrode with molybdenum, -)
: H+, "tll, copper on the entire surface of the semiconductor wafer including the ligature,
Forming a 7b gold plate with good plating properties, and forming a plating resist on parts other than the electrodes -1: me 1 (1: , jiji (f3
K Metsuki K Formation lj method.
JP57142933A 1982-08-18 1982-08-18 Forming method for solder bump Granted JPS5932154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57142933A JPS5932154A (en) 1982-08-18 1982-08-18 Forming method for solder bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57142933A JPS5932154A (en) 1982-08-18 1982-08-18 Forming method for solder bump

Publications (2)

Publication Number Publication Date
JPS5932154A true JPS5932154A (en) 1984-02-21
JPH0226780B2 JPH0226780B2 (en) 1990-06-12

Family

ID=15327015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57142933A Granted JPS5932154A (en) 1982-08-18 1982-08-18 Forming method for solder bump

Country Status (1)

Country Link
JP (1) JPS5932154A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6226544U (en) * 1985-07-30 1987-02-18
JPH0290622A (en) * 1988-09-28 1990-03-30 Seiko Instr Inc Gold bump forming method
US5175609A (en) * 1991-04-10 1992-12-29 International Business Machines Corporation Structure and method for corrosion and stress-resistant interconnecting metallurgy
US5266522A (en) * 1991-04-10 1993-11-30 International Business Machines Corporation Structure and method for corrosion and stress-resistant interconnecting metallurgy
JPH07201871A (en) * 1993-12-10 1995-08-04 Internatl Business Mach Corp <Ibm> Method for forming metallic contact

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5224466A (en) * 1975-08-20 1977-02-23 Matsushita Electric Ind Co Ltd Semiconductor electrode formation method
JPS52102670A (en) * 1976-02-25 1977-08-29 Hitachi Ltd Formation of extruding electrode in semiconductor device
JPS5469382A (en) * 1977-11-14 1979-06-04 Nec Corp Production of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5224466A (en) * 1975-08-20 1977-02-23 Matsushita Electric Ind Co Ltd Semiconductor electrode formation method
JPS52102670A (en) * 1976-02-25 1977-08-29 Hitachi Ltd Formation of extruding electrode in semiconductor device
JPS5469382A (en) * 1977-11-14 1979-06-04 Nec Corp Production of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6226544U (en) * 1985-07-30 1987-02-18
JPH0290622A (en) * 1988-09-28 1990-03-30 Seiko Instr Inc Gold bump forming method
US5175609A (en) * 1991-04-10 1992-12-29 International Business Machines Corporation Structure and method for corrosion and stress-resistant interconnecting metallurgy
US5266522A (en) * 1991-04-10 1993-11-30 International Business Machines Corporation Structure and method for corrosion and stress-resistant interconnecting metallurgy
US5442239A (en) * 1991-04-10 1995-08-15 International Business Machines Corporation Structure and method for corrosion and stress-resistant interconnecting metallurgy
JPH07201871A (en) * 1993-12-10 1995-08-04 Internatl Business Mach Corp <Ibm> Method for forming metallic contact

Also Published As

Publication number Publication date
JPH0226780B2 (en) 1990-06-12

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