JPS6152984B2 - - Google Patents
Info
- Publication number
- JPS6152984B2 JPS6152984B2 JP52093782A JP9378277A JPS6152984B2 JP S6152984 B2 JPS6152984 B2 JP S6152984B2 JP 52093782 A JP52093782 A JP 52093782A JP 9378277 A JP9378277 A JP 9378277A JP S6152984 B2 JPS6152984 B2 JP S6152984B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- forming
- tungsten film
- tungsten
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 35
- 229910052721 tungsten Inorganic materials 0.000 claims description 35
- 239000010937 tungsten Substances 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 238000007747 plating Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 19
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 17
- 239000010931 gold Substances 0.000 claims description 17
- 229910052737 gold Inorganic materials 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 239000000463 material Substances 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 235000006408 oxalic acid Nutrition 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Landscapes
- Weting (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】
本発明は金属パターン形成方法に関し、特に多
層の金属パターンの形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a metal pattern, and more particularly to a method for forming a multilayer metal pattern.
従来、金属パターン形成の有効な一方法として
メツキ法が知られている。メツキ法では任意の膜
厚が簡単に得られることや被メツキ基板の段部で
の被覆性が良いことなどの特徴を有しており、半
導体装置などでも広く用いられている。 Conventionally, a plating method has been known as an effective method for forming metal patterns. The plating method has features such as being able to easily obtain a desired film thickness and providing good coverage of stepped portions of the plated substrate, and is widely used in semiconductor devices and the like.
従来より一般に採用されているメツキ法を説明
すると、先ず基板表面に一様連続的に被着された
鍍金性物質表面に選択的に難鍍金性物質例えばア
ルミナ等の酸化物を形成し、しかる後メツキ処理
を施すと鍍金性物質の露出面にのみ金属メツキ層
が形成される。次に、難鍍金性物質及びその下の
鍍金性物質を除去すれば不連続的金属パターンが
形成できる。しかし、このとき用いられる鍍金性
物質は一般には白金やタングステン等の難加工性
物質であるためその選択的除去は容易でない。ま
た、この物質の蝕刻処理中にメツキ金属も同時に
蝕刻されるなどの困難が伴なう。その結果所望の
不連続的金属パターンは得難い欠点がある。 To explain the plating method that has been generally adopted in the past, first, a difficult-to-plated material, such as an oxide such as alumina, is selectively formed on the surface of a plating material that is uniformly and continuously deposited on the substrate surface, and then When plating is performed, a metal plating layer is formed only on the exposed surface of the plating material. Next, a discontinuous metal pattern can be formed by removing the difficult-to-plated material and the plating-prone material thereunder. However, since the plating material used at this time is generally a difficult-to-process material such as platinum or tungsten, its selective removal is not easy. Further, during the etching process of this material, the plating metal is also etched at the same time, which is accompanied by difficulties. As a result, the desired discontinuous metal pattern is difficult to obtain.
メツキ法に関しては次のような別の方法があ
る。先ず基板表面にホトレジストでパターンを形
成した後、該ホトレジストパターンを含む基板表
面に鍍金性物質を被着させる。次に、ホトレジス
トを剥離して該ホトレジスト上の鍍金性物質を除
去して鍍金性物質の不連続パターンを得る。次
に、基板表面全体に導電性物質を被着させた後、
ホトレジストをマスクとして導電性物質を選択除
去する。このときには前記鍍金性物質の大部分が
露出し、しかも鍍金性物質と導電性物質とで連続
体を形成するような選択除去が行なわれる。しか
る後メツキ処理を施せば鍍金性物質の露出面に金
属がメツキされる。次にホトレジスト及び導電性
物質を除去すれば良い。この方法では難加工性の
鍍金性物質はリフト・オフ法を用いて比較的簡単
に所望の不連続パターンが得られるが、この不連
続パターンの大部分を露出させ、かつ導電性物質
によつて連結体とする作業は煩雑であり、微細な
パターンも得難い欠点がある。 Regarding the Metsuki method, there are other methods as follows. First, a pattern is formed on the surface of a substrate using photoresist, and then a plating material is applied to the surface of the substrate including the photoresist pattern. Next, the photoresist is peeled off and the plating material on the photoresist is removed to obtain a discontinuous pattern of the plating material. Next, after depositing a conductive substance on the entire surface of the substrate,
The conductive material is selectively removed using photoresist as a mask. At this time, selective removal is performed such that most of the plating material is exposed and the plating material and the conductive material form a continuous body. After that, a plating process is performed to plate the exposed surface of the plating material with metal. Next, the photoresist and conductive material may be removed. With this method, the desired discontinuous pattern can be obtained relatively easily by using the lift-off method for difficult-to-process plating materials, but most of this discontinuous pattern is exposed and the conductive material is The process of forming a connected body is complicated, and it is difficult to obtain a fine pattern.
本発明は上記欠点を除き、微細でしかも高信頼
性の不連続的金属パターンを容易に実現する方法
を提供するものである。 The present invention eliminates the above drawbacks and provides a method for easily realizing a fine and highly reliable discontinuous metal pattern.
本発明は、半導体基板上に金属膜と該金属膜表
面の金属酸化膜を形成する工程と、これら両膜の
うち、後に配線路となる領域を選択的に除去する
工程と、前記半導体基板に一部被着し、かつ除去
された部分に露出せる前記金属膜に被着せる第１
のタングステン膜を形成する工程と、前記金属膜
を電流路として前記第１のタングステン膜上に第
１の金層をメツキにより形成する工程と、前記金
属膜上の前記金属酸化膜の上に突出せる前記第１
の金層の露出面に第２のタングステン膜を形成す
る工程と、前記金属膜および前記金属酸化膜を除
去する工程と、全体をシリコン酸化膜により被覆
し、該シリコン酸化膜に前記第２のタングステン
膜に達する開孔を形成する工程と、前記シリコン
酸化膜上に被着し前記開孔を通して前記第２のタ
ングステン膜に接続せる第３のタングステン膜を
選択的に形成する工程と、前記第３のタングステ
ン膜上に第２の金層を形成する工程とを有し、前
記第１のタングステン膜、前記第２のタングステ
ン膜および前記第１の金層を前記半導体基板に接
続せる第１の配線路とし、前記第３のタングステ
ン膜および前記第２の金層を前記第１の配線路に
接続する第２の配線路としたことを特徴とする金
属パターンの製造方法である。 The present invention includes a step of forming a metal film and a metal oxide film on the surface of the metal film on a semiconductor substrate, a step of selectively removing a region of these films that will later become a wiring path, and a step of forming a metal film on the semiconductor substrate. A first layer deposited on the metal film partially deposited and exposed on the removed portion.
forming a first gold layer on the first tungsten film by plating, using the metal film as a current path, and protruding onto the metal oxide film on the metal film. The first
forming a second tungsten film on the exposed surface of the gold layer; removing the metal film and the metal oxide film; covering the entire surface with a silicon oxide film; forming an opening that reaches the tungsten film; selectively forming a third tungsten film that is deposited on the silicon oxide film and connected to the second tungsten film through the opening; forming a second gold layer on the tungsten film of No. 3, and connecting the first tungsten film, the second tungsten film, and the first gold layer to the semiconductor substrate. The method of manufacturing a metal pattern is characterized in that the third tungsten film and the second gold layer are used as a second wiring path connecting the first wiring path.
本発明を半導体装置の配線路に適用した実施例
を用いて説明する。 The present invention will be explained using an example in which the present invention is applied to a wiring path of a semiconductor device.
説明を簡単にするため、現在最も一般的に使用
されている材料、即ち半導体としてシリコン、導
電性の金属膜としてアルミニウムを用いた場合に
ついて説明する。 To simplify the explanation, a case will be described in which the most commonly used materials at present, that is, silicon is used as the semiconductor and aluminum is used as the conductive metal film.
第１図は本発明の実施例の製造工程断面図であ
る。先ず、シリコン基板１１表面に設けた所望の
開孔を有するシリコン酸化膜１２の表面にアルミ
ニウム１３を被着させた後陽極酸化処理を施し前
記アルミニウム１３の表面に難鍍金性物質として
アルミナ１４を形成する（第１図ａ）。 FIG. 1 is a sectional view of the manufacturing process of an embodiment of the present invention. First, aluminum 13 is deposited on the surface of a silicon oxide film 12 having desired openings provided on the surface of a silicon substrate 11, and then anodic oxidation treatment is performed to form alumina 14 as a difficult-to-plated substance on the surface of the aluminum 13. (Figure 1a).
次に、ホトレジスト法により配線路部と逆パタ
ーンのホトレジストパターン１５を設け前記アル
ミニウム１３及びアルミナ１４を蝕刻する（第１
図ｂ）。 Next, a photoresist pattern 15 having a pattern opposite to that of the wiring path portion is provided by a photoresist method, and the aluminum 13 and alumina 14 are etched (first
Figure b).
次に、ホトレジストパターン１５を含む半導体
基板１１表面にタングステンを被着させた後、ホ
トレジストを剥離するとホトレジストパターン１
５と逆パターン即ち配線路部分にタングステン膜
１６が形成される。このときタングステン膜１６
はアルミニウム１３の側面に付着するため自己整
合的に両者は連続体を形成する。一方、ホトレジ
スト１５とアルミナ１４、及びアルミナ１４とア
ルミニウム１３とでそれぞれ梁が形成され、その
部分でのタングステン膜が薄くなるため、タング
ステン膜のリフト・オフが安定確実に行なえる
（第１図ｃ）。 Next, after depositing tungsten on the surface of the semiconductor substrate 11 including the photoresist pattern 15, when the photoresist is peeled off, the photoresist pattern 1
A tungsten film 16 is formed in a pattern opposite to 5, that is, in a wiring path portion. At this time, the tungsten film 16
is attached to the side surface of the aluminum 13, so that the two form a continuous body in a self-aligned manner. On the other hand, beams are formed by the photoresist 15 and the alumina 14, and by the alumina 14 and the aluminum 13, and the tungsten film becomes thinner in those areas, so that the tungsten film can be lifted off stably and reliably (Fig. 1c). ).
次に、この半導体基板に金メツキ処理を施すと
鍍金性物質１６の表面にのみ金層１７が成長する
（第１図ｄ）。 Next, when this semiconductor substrate is subjected to gold plating, a gold layer 17 grows only on the surface of the plating material 16 (FIG. 1d).
次に、基板表面にタングステン２８を被着さ
せ、しかる後アルミニウム１３及びアルミナ１４
を蝕刻して、配線路の表面にタングステン膜２８
を形成する（第１図ｅ）。 Next, tungsten 28 is deposited on the surface of the substrate, and then aluminum 13 and alumina 14 are deposited.
A tungsten film 28 is etched on the surface of the wiring path.
(Fig. 1e).
アルミニウム１３及びアルミナ１４の蝕刻には
一般にリン酸が用いられ、この蝕刻液に対しては
タングステン及び金はともに蝕刻されず配線路は
安定して得られる。アルミニウム１３の膜厚はメ
ツキ時に通電し得る程度有れば良く0.4μｍ程度
が好ましく、アルミナ１４の形成には２％蓚酸水
溶液中5Vで５分間陽極酸化するのが実用上好適
である。 Phosphoric acid is generally used for etching the aluminum 13 and alumina 14, and neither tungsten nor gold is etched with this etching solution, and wiring paths can be stably obtained. The thickness of the aluminum 13 is preferably about 0.4 μm as long as it can conduct electricity during plating, and it is practically preferable to form the alumina 14 by anodic oxidation in a 2% oxalic acid aqueous solution at 5 V for 5 minutes.
また、タングステン膜１６は基板材料のシリコ
ンと配線材料の金との合金反応を阻止することを
目的としその膜厚は実用上0.2μｍ程度が好適で
ある。 Further, the tungsten film 16 is intended to prevent an alloy reaction between silicon, which is a substrate material, and gold, which is a wiring material, and the film thickness is practically preferably about 0.2 μm.
次に、この配線路を含む基板表面に電気絶縁
物、例えば気相成長シリコン酸化膜２９を被着さ
せた後、該シリコン酸化膜２９に所望の開孔３０
を設ける。このときのタングステン膜２８は、下
の配線路とシリコン酸化膜２９との密着強度の改
善を目的とし、その膜厚は500Åあれば良い（第
１図ｆ）。 Next, an electrical insulator such as a vapor-grown silicon oxide film 29 is deposited on the surface of the substrate including the wiring path, and then a desired opening 30 is formed in the silicon oxide film 29.
will be established. The purpose of the tungsten film 28 at this time is to improve the adhesion strength between the underlying wiring path and the silicon oxide film 29, and its film thickness may be 500 Å (FIG. 1f).
しかる後、タングステン膜３１、金層３２、か
らなる第２層目の配線路を形成するのであるが、
その製造方法は、第１図ａ〜ｅに示した配線路の
製造方法と同一の手法をくり返せば良い。これに
より第２層配線路を形成する（第１図ｇ）。 After that, a second layer of wiring path consisting of a tungsten film 31 and a gold layer 32 is formed.
The manufacturing method thereof may be repeated by repeating the same method as the wiring path manufacturing method shown in FIGS. 1a to 1e. This forms a second layer wiring path (FIG. 1g).
第１図は本発明の実施例の製造工程断面図であ
る。
１１…シリコン基板、１２…シリコン酸化膜、
１３…アルミニウム、１４…アルミナ、１５…ホ
トレジスト、１６…タングステン膜、１７…金、
２８…タングステン膜、２９…シリコン酸化膜、
３０…開口、３１…タングステン膜、３２…金。
FIG. 1 is a sectional view of the manufacturing process of an embodiment of the present invention. 11... Silicon substrate, 12... Silicon oxide film,
13... Aluminum, 14... Alumina, 15... Photoresist, 16... Tungsten film, 17... Gold,
28...Tungsten film, 29...Silicon oxide film,
30...Opening, 31...Tungsten film, 32...Gold.
Claims (1)
酸化膜を形成する工程と、これら両膜のうち、後
に配線路となる領域を選択的に除去する工程と、
前記半導体基板に一部被着し、かつ除去された部
分に露出せる前記金属膜に被着せる第１のタング
ステン膜を形成する工程と、前記金属膜を電流路
として前記第１のタングステン膜上に第１の金層
をメツキにより形成する工程と、前記金属膜上の
前記金属酸化膜の上に突出せる前記第１の金層の
露出面に第２のタングステン膜を形成する工程
と、前記金属膜および前記金属酸化膜を除去する
工程と、全体をシリコン酸化膜により被覆し、該
シリコンン酸化膜に前記第２のタングステン膜に
達する開孔を形成する工程と、前記シリコン酸化
膜上に被着し前記開孔を通して前記第２のタング
ステン膜に接続せる第３のタングステン膜を選択
的に形成する工程と、前記第３のタングステン膜
上に第２の金層を形成する工程とを有し、前記第
１のタングステン膜、前記第２のタングステン膜
および前記第１の金層を前記半導体基板に接続せ
る第１の配線路とし、前記第３のタングステン膜
および前記第２の金層を前記第１の配線路に接続
する第２の配線路としたことを特徴とする金属パ
ターンの製造方法。1. A step of forming a metal film and a metal oxide film on the surface of the metal film on a semiconductor substrate, and a step of selectively removing a region of both films that will later become a wiring path,
a step of forming a first tungsten film to be deposited on the metal film partially deposited on the semiconductor substrate and exposed in the removed portion, and forming a first tungsten film on the first tungsten film using the metal film as a current path forming a first gold layer by plating; forming a second tungsten film on the exposed surface of the first gold layer that protrudes above the metal oxide film on the metal film; a step of removing the film and the metal oxide film, a step of covering the whole with a silicon oxide film, forming an opening in the silicon oxide film reaching the second tungsten film, and a step of covering the silicon oxide film. selectively forming a third tungsten film to be connected to the second tungsten film through the opening, and forming a second gold layer on the third tungsten film. , the first tungsten film, the second tungsten film, and the first gold layer are connected to the semiconductor substrate as a first wiring path, and the third tungsten film and the second gold layer are connected to the semiconductor substrate. A method for manufacturing a metal pattern, characterized in that a second wiring path is connected to the first wiring path.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9378277A JPS5427771A (en) | 1977-08-04 | 1977-08-04 | Production of metal patterns |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9378277A JPS5427771A (en) | 1977-08-04 | 1977-08-04 | Production of metal patterns |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5427771A JPS5427771A (en) | 1979-03-02 |
| JPS6152984B2 true JPS6152984B2 (en) | 1986-11-15 |
Family
ID=14091975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9378277A Granted JPS5427771A (en) | 1977-08-04 | 1977-08-04 | Production of metal patterns |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5427771A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57191085A (en) * | 1981-05-20 | 1982-11-24 | Mitsubishi Paper Mills Ltd | Ordinary paper transfer type pressure sensitive copying paper |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS611888A (en) * | 1984-06-14 | 1986-01-07 | Matsushita Electric Ind Co Ltd | Refrigerant compressor |
-
1977
- 1977-08-04 JP JP9378277A patent/JPS5427771A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS611888A (en) * | 1984-06-14 | 1986-01-07 | Matsushita Electric Ind Co Ltd | Refrigerant compressor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5427771A (en) | 1979-03-02 |
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