JPS6248899B2 - - Google Patents
Info
- Publication number
- JPS6248899B2 JPS6248899B2 JP56084025A JP8402581A JPS6248899B2 JP S6248899 B2 JPS6248899 B2 JP S6248899B2 JP 56084025 A JP56084025 A JP 56084025A JP 8402581 A JP8402581 A JP 8402581A JP S6248899 B2 JPS6248899 B2 JP S6248899B2
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- plating
- wiring pattern
- forming
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229920002120 photoresistant polymer Polymers 0.000 claims description 47
- 238000007747 plating Methods 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000007429 general method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかり、主に
テープキヤリヤ式集積回路の製造方法に関するも
のであり、特に配線の微細化，多層化，歩留りの
向上に有力な効果を発揮する金属配線及び突起電
極の形成方法に関するものである。[Detailed Description of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and mainly relates to a method of manufacturing a tape carrier type integrated circuit, and is particularly effective in miniaturizing wiring, multilayering, and improving yield. The present invention relates to a method for forming metal wiring and protruding electrodes.
一般に第１のフオトレジストによりパターンを
形成し、これをマスクとして第１のメツキにより
金属配線を形成し、第２のフオトレジストにより
突起電極用パターンを形成し、第２のメツキによ
つて金属突起電極を形成する方式の従来技術にか
かる半導体装置の製法においては、第１のフオト
レジスト層が第１のメツキ厚より薄くなつてい
る。したがつて第１のメツキを行なう過程でメツ
キ厚がフオトレジスト厚を越えた時点からメツキ
の成長が等方向となり、メツキ終了時点でのメツ
キの断面形状がオーバーハング状となる。この様
な基板にフオトレジストを被着し、第１のメツキ
配線上の一部分に第２のメツキを行なおうとする
と、オーバーハング部分をフオトレジストが十分
に覆えず、第１のメツキの端部にピンホールが発
生しやすくなる。このため、従来の方法によると
第２のメツキ時に第１のメツキの端部のピンホー
ルから第２のメツキが成長し、これにより歩留り
の低下をもたらすことがしばしばあつた。 Generally, a pattern is formed using a first photoresist, using this as a mask, metal wiring is formed using the first plating, a pattern for protruding electrodes is formed using a second photoresist, and metal protrusions are formed using the second plating. In the method of manufacturing a semiconductor device according to the conventional technique of forming an electrode, the first photoresist layer is thinner than the first plating thickness. Therefore, from the time when the plating thickness exceeds the photoresist thickness in the process of performing the first plating, the plating grows in the same direction, and the cross-sectional shape of the plating becomes overhanging when the plating is completed. When a photoresist is applied to such a board and a second plating is applied to a part of the first plating wiring, the photoresist cannot sufficiently cover the overhanging part, and the end of the first plating is pinholes are more likely to occur. For this reason, according to the conventional method, the second plating grows from the pinhole at the end of the first plating during the second plating, which often results in a decrease in yield.
この様なピンホールを低減させる方法として、
第２のフオトレジストの厚さを十分厚くしてオー
バーハングを覆う方法が従来から行なわれている
が、この方法によると第２のフオトレジストを極
めて厚くする必要があり、第２のフオトレジス
トパターンの微細化が困難、フオトレジストプ
ロセスにおける露光時間が極めて長く必要となり
生産性が悪い、上記の欠点を補うため２重にフ
オトレジストのパターニングを行なうと工程が複
雑化し、歩留り・生産性が悪い等の種々の欠点が
あつた。 As a method to reduce such pinholes,
A conventional method has been to make the second photoresist sufficiently thick to cover the overhang, but with this method, it is necessary to make the second photoresist extremely thick, and the second photoresist pattern It is difficult to miniaturize the photoresist process, the exposure time in the photoresist process is extremely long, resulting in poor productivity.Double patterning of photoresist to compensate for the above drawbacks complicates the process, resulting in poor yield and productivity, etc. There were various shortcomings.
本発明は上記の様な欠点を除き、メツキによる
金属配線及び突起電極を歩留りよく形成する方法
を提供するものである。 The present invention eliminates the above-mentioned drawbacks and provides a method for forming metal wiring and protruding electrodes by plating with a high yield.
本発明によれば第１のメツキの端部での第２の
フオトレジストのピンホールの発生を極めてわず
かにすることが可能であり、かつ第２のフオトレ
ジスト厚を厚くする必要がないので生産性も向上
できる。 According to the present invention, it is possible to minimize the occurrence of pinholes in the second photoresist at the ends of the first plating, and there is no need to increase the thickness of the second photoresist, which facilitates production. It can also improve your sex.
本発明の特徴は、半導体基板上に第１の配線パ
ターンを形成する工程と、前記半導体基板上に第
１のフオトレジストパターンを形成する工程と、
前記第１のフオトレジストをマスクとして第１の
メツキを行いこれにより該第１のフオトレジスト
の厚さと厚さが同じか又は厚さがより薄い第２の
配線パターンを前記第１の配線パターン上に該第
１の配線パターンより小さい巾寸法をもつて形成
する工程と、前記第１のフオトレジストを除去す
る工程と、前記第１および第２の配線パターンの
露出せる側面および上面に該第２の配線パターン
よりも薄い膜厚の第２のフオトレジストを被着す
る工程と、前記第２の配線パターンの上面の所定
部分を露出せる開口を前記第２のフオトレジスト
に形成する工程と、前記第２のフオトレジストを
マスクとして第２のメツキにより前記開口におい
て前記金属線の上面に被着しかつ前記第２のフオ
トレジストよりも上部に突出せる金属突起電極を
形成する工程とを含む半導体装置の製造方法にあ
る。本発明の方法によれば、第１のフオトレジス
トパターンを形成しこれにより第２の配線パター
ンを形成する前に第１の配線パターンがすでに形
成されている。したがつて第１の配線パターンと
第２の配線パターンとの材質は関係は自由に選択
できる。すなわち第２の配線パターンをマスクと
して第１の配線パターンを形成するようなもので
はないから両者のエツチング特性を考える必要が
ない。又、第１と第２の配線パターン間には段部
を形成できるから金属突起電極に加わる力が半導
体基板に伝えられる際のクツシヨン作用の形状と
することができる。第１のフオトレジストは第１
のメツキ処理によりその表面に第１のメツキの金
属粒が付着している。したがつてこの上に第２の
フオトレジストを付着すると両者間の密着性が悪
くなつているから第２のメツキの際に不所望の個
所に第２のメツキ金属が付着してしまうしかるに
本発明では第１のフオトレジストを除去するから
そのような不都合は生じない。 The present invention is characterized by a step of forming a first wiring pattern on a semiconductor substrate, a step of forming a first photoresist pattern on the semiconductor substrate,
First plating is performed using the first photoresist as a mask, thereby forming a second wiring pattern on the first wiring pattern, the thickness of which is equal to or thinner than that of the first photoresist. forming the first wiring pattern to have a width smaller than that of the first wiring pattern, removing the first photoresist, and forming the second wiring pattern on the exposed side and top surfaces of the first and second wiring patterns. forming an opening in the second photoresist to expose a predetermined portion of the upper surface of the second wiring pattern; using a second photoresist as a mask to form a metal protrusion electrode that adheres to the upper surface of the metal wire in the opening and protrudes above the second photoresist by second plating. It is in the manufacturing method. According to the method of the present invention, the first wiring pattern is already formed before forming the first photoresist pattern and thereby forming the second wiring pattern. Therefore, the relationship between the materials of the first wiring pattern and the second wiring pattern can be freely selected. That is, since the first wiring pattern is not formed using the second wiring pattern as a mask, there is no need to consider the etching characteristics of both. Further, since a stepped portion can be formed between the first and second wiring patterns, it is possible to form a shape that acts as a cushion when the force applied to the metal protrusion electrode is transmitted to the semiconductor substrate. The first photoresist is the first photoresist.
As a result of the plating process, the metal grains of the first plating are attached to the surface. Therefore, if a second photoresist is applied on top of this, the adhesion between the two will deteriorate, and the second plating metal will adhere to undesired areas during the second plating.However, the present invention Since the first photoresist is removed, such inconvenience does not occur.
次に本発明を実施例により説明する。第１図〜
第６図は本発明をテーブキヤリア式集積回路の金
メツキ配線及び金突起電極の形成に適用した場合
の断面図である。 Next, the present invention will be explained by examples. Figure 1~
FIG. 6 is a sectional view when the present invention is applied to the formation of gold-plated wiring and gold protrusion electrodes of a table carrier type integrated circuit.
第１図において、一般の方法で素子を形成済の
半導体基板１の上にエツチング法又はリフトオフ
法等でパターニングされた白金の配線パターン２
が設けられている。この基板上に第１のフオトレ
ジストを被着し、これを通常の方法で所望の形状
にパターン形成して、フオトレジストパターン３
を形成する（第２図）。このフオトレジスト３の
厚さは後述の第１の金メツキで予定されているメ
ツキ厚よりも厚いか同じになるように予めフオト
レジストの被着条件を設定しておく。この後、該
基板を金メツキ液に浸漬し、基板とメツキ液間に
電流を流して所望の厚さまでメツキ４を行なう
（第３図）。この時、メツキ４の厚さは第１のフオ
トレジスト３の厚さよりも小さいか同じであるた
め、メツキの断面形状はフオトレジストの断面形
状に依存し、オーバーハング状となることはな
い。次に第１のフオトレジスト３を除去し該基板
上に更に第２のフオトレジストを被着し、通常の
方法でパターン形成してフオトレジストパターン
５を形成する（第４図）。この時、第１のメツキ
の断面形状はオーバーハング状とはなつていない
ので、比較的薄く被着してもピンホールが発生す
ることがない。この後、該基板を通常の方法で金
メツキを行なつて金突起電極６を形成し（第５
図）、さらにフオトレジストを全部除去すれば所
望の形状の金配線及び金突起電極を形成すること
ができる（第６図）。 In FIG. 1, a platinum wiring pattern 2 is patterned by an etching method or a lift-off method on a semiconductor substrate 1 on which elements have already been formed by a general method.
is provided. A first photoresist is deposited on this substrate and patterned into a desired shape by a conventional method to form a photoresist pattern 3.
(Figure 2). Conditions for depositing the photoresist are set in advance so that the thickness of the photoresist 3 is greater than or equal to the plating thickness planned for the first gold plating to be described later. Thereafter, the substrate is immersed in a gold plating solution, and a current is passed between the substrate and the plating solution to perform plating 4 to a desired thickness (FIG. 3). At this time, since the thickness of the plating 4 is smaller than or equal to the thickness of the first photoresist 3, the cross-sectional shape of the plating depends on the cross-sectional shape of the photoresist, and there is no overhang. Next, the first photoresist 3 is removed, and a second photoresist is deposited on the substrate and patterned in a conventional manner to form a photoresist pattern 5 (FIG. 4). At this time, since the cross-sectional shape of the first plating does not have an overhang shape, pinholes will not occur even if it is applied relatively thinly. Thereafter, gold plating is performed on the substrate in a usual manner to form gold protrusion electrodes 6 (fifth
Furthermore, by removing all the photoresist, it is possible to form gold wiring and gold protrusion electrodes in a desired shape (FIG. 6).
以上は本発明をテープキヤリア式集積回路の金
メツキ配線及び金突起電極の形成に適用した場合
の方法について述べたが、その他の半導体装置及
びその他の金属のメツキにより配線を形成する場
合も同様に実施できることは明らかである。 The above has described the method in which the present invention is applied to the formation of gold-plated wiring and gold protrusion electrodes for tape carrier type integrated circuits, but the same applies to the formation of wiring by plating of other semiconductor devices and other metals. It is clear that it can be done.
以上説明した様に本発明によればメツキ配線を
有する半導体装置を歩留り良くかつ生産性高く製
造することができる。 As explained above, according to the present invention, a semiconductor device having plated wiring can be manufactured with high yield and productivity.
第１図乃至第６図は本発明の実施例を製造工程
順に示した断面図である。
尚、図において、１……素子を形成済の半導体
基板、２……リフトオフ法等で形成された基板１
上の白金配線パターン、３……所望の形状にパタ
ーニングされた第１のフオトレジスト、４……第
１のメツキ、５……所望の形状にパターニングさ
れた第２のフオトレジスト、６……第２のメツキ
である。
FIGS. 1 to 6 are cross-sectional views showing embodiments of the present invention in the order of manufacturing steps. In the figure, 1...a semiconductor substrate on which elements have been formed, 2...a substrate 1 formed by a lift-off method, etc.
Upper platinum wiring pattern, 3... First photoresist patterned into a desired shape, 4... First plating, 5... Second photoresist patterned into a desired shape, 6... First photoresist patterned into a desired shape. This is No. 2 Metsuki.
Claims (1)
る工程と、前記半導体基板上に第１のフオトレジ
ストパターンを形成する工程と、前記第１のフオ
トレジストをマスクとして第１のメツキを行いこ
れにより該第１のフオトレジストの厚さと厚さが
同じか又は厚さがより薄い第２の配線パターンを
前記第１の配線パターン上に該第１の配線パター
ンより小さい巾寸法をもつて形成する工程と、前
記第１のフオトレジストを除去する工程と、前記
第１および第２のパターンの露出せる側面および
上面に該第２の配線パターンよりも薄い膜厚の第
２のフオトレジストを被着する工程と、前記第２
の配線パターンの上面の所定部分を露出せる開口
を前記第２のフオトレジストに形成する工程と、
前記第２のフオトレジストをマスクとして第２の
メツキにより前記開口において前記金属配線の上
面に被着しかつ前記第２のフオトレジストよりも
上部に突出せる金属突起電極を形成する工程とを
含むことを特徴とする半導体装置の製造方法。1. A step of forming a first wiring pattern on a semiconductor substrate, a step of forming a first photoresist pattern on the semiconductor substrate, and performing a first plating using the first photoresist as a mask. forming a second wiring pattern on the first wiring pattern, the second wiring pattern having the same thickness as the first photoresist or having a smaller width than the first wiring pattern; and a step of removing the first photoresist, and depositing a second photoresist having a thickness thinner than that of the second wiring pattern on the exposed side surfaces and top surfaces of the first and second patterns. step, and the second
forming an opening in the second photoresist to expose a predetermined portion of the upper surface of the wiring pattern;
forming a metal protrusion electrode that adheres to the upper surface of the metal wiring in the opening and projects above the second photoresist by second plating using the second photoresist as a mask; A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56084025A JPS57198648A (en) | 1981-06-01 | 1981-06-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56084025A JPS57198648A (en) | 1981-06-01 | 1981-06-01 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57198648A JPS57198648A (en) | 1982-12-06 |
| JPS6248899B2 true JPS6248899B2 (en) | 1987-10-16 |
Family
ID=13819011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56084025A Granted JPS57198648A (en) | 1981-06-01 | 1981-06-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57198648A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52120683A (en) * | 1976-03-31 | 1977-10-11 | Licentia Gmbh | Method of making multiilayered metalic electrodes for semiconductor elements |
| JPS52128059A (en) * | 1976-04-20 | 1977-10-27 | Nec Corp | Manufacture of semiconductor device |
-
1981
- 1981-06-01 JP JP56084025A patent/JPS57198648A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52120683A (en) * | 1976-03-31 | 1977-10-11 | Licentia Gmbh | Method of making multiilayered metalic electrodes for semiconductor elements |
| JPS52128059A (en) * | 1976-04-20 | 1977-10-27 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57198648A (en) | 1982-12-06 |
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