JPS5931085A - Manufacture of semiconductor laser - Google Patents

Manufacture of semiconductor laser

Info

Publication number
JPS5931085A
JPS5931085A JP57141407A JP14140782A JPS5931085A JP S5931085 A JPS5931085 A JP S5931085A JP 57141407 A JP57141407 A JP 57141407A JP 14140782 A JP14140782 A JP 14140782A JP S5931085 A JPS5931085 A JP S5931085A
Authority
JP
Japan
Prior art keywords
semiconductor laser
silicon
gold
chip
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57141407A
Other languages
Japanese (ja)
Other versions
JPH0140514B2 (en
Inventor
Yoshito Ikuwa
生和　義人
Shoichi Kakimoto
柿本　昇一
Shigeyuki Nitsuta
仁田　重之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57141407A priority Critical patent/JPS5931085A/en
Publication of JPS5931085A publication Critical patent/JPS5931085A/en
Publication of JPH0140514B2 publication Critical patent/JPH0140514B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H01S5/0237—Fixing laser chips on mounts by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To enable to braze a semiconductor laser chip to an Si sub mount and a metallic block at the same time by a method wherein an Au plated film is provided previously on the main surface whereon the semiconductor laser chip is enabled to be brazed. CONSTITUTION:The Si sub mount 1' is mounted on the Ag block 3, and the semiconductor laser chip 2' is mounted on the sub mount 1'. Au plated films 15-17 are formed respectively on the brazing surfaces of the sub mount 1' and the laser chip 2'. When these elements successively mounted are heated, the platings 15-17 on each junction surface fuse, resulting in connection each other. Thereby, the semiconductor laser element, Si sub mount, and metallic block can be brazed at the same time; therefore the yield of the laser device and the workability of the manufacture can be contrived to improve.

Description

【発明の詳細な説明】 本発明は、半導体レーザ装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor laser device.

半導体レーザのチップは、動作中に発生する熱の放出を
良くシ、かつ、ハンドリングを容易にするため、銀等の
ブロックにろう付けされる。信頼性を考えた時、このろ
う材としては、金・シリコンろう等を使用するのが良い
。しかし、金・シリコンろう材は硬質であるため、チッ
プをブロックに金・シリコンろう材を介して直接ろう付
けすると、チップとブロックの熱膨張率の遣いによりチ
ップにひずみが発生し易く、レーザ特性が悪くなり易い
。これを防止するために、シリコン板（以後シリコンサ
ブマクントと称す）をチップとブロックの間にはさんで
ろう付けする方法がしばしば行なわれる。Semiconductor laser chips are soldered to a block made of silver or the like in order to better dissipate heat generated during operation and to facilitate handling. When considering reliability, it is best to use gold or silicone brazing material as this brazing material. However, since the gold/silicon brazing material is hard, if the chip is brazed directly to the block via the gold/silicon brazing material, the chip is likely to become distorted due to the difference in thermal expansion coefficient between the chip and the block, and the laser characteristics tends to get worse. To prevent this, a method is often used in which a silicon plate (hereinafter referred to as a silicon submact) is sandwiched between the chip and the block and brazed.

従来のこのチップ、シリコンサブマクント、およびブロ
ックのろう付けは、第１図（ａ）に示すように例えば両
面に約２μｍの金メッキ膜０１）を有する厚み８００μ
ｍのシリコンサブマクント（１）を先ず第１図（ｂ）に
示すように４８０℃の窒素雰囲気中に置き、シリコンサ
ブマウント（１）の材料であるシリコン０．２とメッキ
された金０１）の共晶により金・シリコンろう材α１を
形成し、チップ（２）をこの共振器面（６）と垂直な面
（７）をピンセットでつかみ前記金・シリコンろう材（
ト）中でシリコンサブマウント（１）にこすることによ
り半導体レーザチップ（２）とシリコンサブマウント（
１）をろう付けし、続いて第１図（Ｃ）に示すように銀
ブロック（３）を４８０℃の窒素雰囲気中に置き、この
銀ブロック（３）のろう付けする位置に金・シリコンろ
う材α荀を溶かしたのち、前記チップ（２）をろう付け
したシリコンサブマウント（１）を金・シリコンろう材
Ｑ４）中で銀ブロック（３）にこすることにより、シリ
コンサブマウント（１）と銀ブロック（３）のろう付け
を行なう。Conventional brazing of this chip, silicon submachine, and block is performed using, for example, a 800 μm thick gold plated film 01) with a gold plating film of about 2 μm on both sides, as shown in FIG. 1(a).
First, as shown in FIG. 1(b), a silicon submount (1) of m is placed in a nitrogen atmosphere at 480°C, and silicon 0.2, which is the material of the silicon submount (1), and plated gold 01 are placed. A gold/silicon brazing material α1 is formed by the eutectic of the gold/silicon brazing material (
The semiconductor laser chip (2) and the silicon submount (1) are rubbed by rubbing it on the silicon submount (1) in
1), then place the silver block (3) in a nitrogen atmosphere at 480°C as shown in Figure 1 (C), and apply gold/silicon solder to the position of the silver block (3) to be brazed. After melting the material α, the silicon submount (1) to which the chip (2) is brazed is rubbed against a silver block (3) in a gold/silicon brazing material Q4) to form a silicon submount (1). and solder the silver block (3).

しかしなから、かかる従来のろう付は方法では次に示す
欠点かあった。However, such conventional brazing methods have the following drawbacks.

１、チップ（２）とシリコンサブマウント（１）のろう
付けの際、チップ（２）は、共振器面に垂直な而（７）
をつかんで共晶にて形成された金・シリコンろう材（至
）中でシリコンサブマウント（１）にこすられるため、
チップ（２）にろう材がつき易くまたチップ（２）の共
振器面に垂直な而（７）が傷つき易い。このため半導体
レーザの特性か悪くなることがある。1. When brazing the chip (2) and the silicon submount (1), the chip (2) must be perpendicular to the resonator plane (7).
Because it is rubbed against the silicon submount (1) in the gold-silicon brazing material (1) formed by eutectic,
The solder metal easily sticks to the chip (2), and the part (7) of the chip (2) that is perpendicular to the resonator surface is easily damaged. Therefore, the characteristics of the semiconductor laser may deteriorate.

２、シリコンサブマウント（１）を銀ブロック（３）Ｋ
ろう付けする時に、先にシリコンサブマウント（１）の
銀ブロック（３）へのろう付と同一温度でシリコンサブ
マウント（１）上にろう付されたチップ（２）が動くこ
とがある。2. Silicon submount (1) with silver block (3) K
During brazing, the chip (2) previously brazed onto the silicon submount (1) at the same temperature as the brazing of the silicon submount (1) to the silver block (3) may move.

本発明は上記従来の半導体レーデ装置のろう付法の欠点
を取除くためになされたものであり、シリコンサブマウ
ント上に半導体レーザ素子を互の金メッキ聞が接するよ
うに載せると共に、半導体レーザ素子が載せられたシリ
コンサブマウントをこの金メッキ而が接するように金属
ブロックに載せ、半導体レーデ素子、シリコンサブマウ
ント及び金属ブロックを同時にろう付し、歩留と作業性
が共に良好な半導体レーデ装置の製造方法を提供する。The present invention has been made in order to eliminate the drawbacks of the conventional brazing method for semiconductor radar devices, and includes mounting a semiconductor laser element on a silicon submount so that the gold plating parts are in contact with each other, and the semiconductor laser element is A method for manufacturing a semiconductor RADE device with good yield and workability by placing the mounted silicon submount on a metal block so that the gold plating is in contact with the semiconductor RADE element, the silicon submount, and the metal block at the same time. I will provide a.

以下、第２図により本発明の一実施例を詳細に説明する
。Hereinafter, one embodiment of the present invention will be described in detail with reference to FIG.

第２図（ａ）は本発明の一実施例の半導体レーデのろう
付けに使用されるシリコンサブマウントの断面図である
。図中（１）はシリコンサブマウント、（イ）は厚さ８
００μｍのシリコン、αυは半導体レーデチップをろう
付けする面に被着された１〜６μｍの厚みの金メッキ膜
、ＱＱは銀ブロックにろう付けされる而に被着された１
０〜２０μｍの厚みの金メッキ膜である。（１′）は前
記Ｑ埠ａＱＱ時からなるシリコンサブマウントである。FIG. 2(a) is a sectional view of a silicon submount used for soldering a semiconductor radar according to an embodiment of the present invention. In the figure, (1) is a silicon submount, (A) is a thickness of 8
00 μm of silicon, αυ is a gold plated film with a thickness of 1 to 6 μm deposited on the surface to which the semiconductor radar chip is brazed, and QQ is the gold plated film deposited on the surface to be brazed to the silver block.
It is a gold-plated film with a thickness of 0 to 20 μm. (1') is a silicon submount consisting of the above-mentioned Q mount aQQ.

ろう付けは先ず第２図（ｂ）に示すように２００℃の窒
素雰囲気中で銀ブロック（３）の上の所定の位置に前記
シリコンサプマクン）　（１’）ヲｔせ、続いてサブマ
ウント（１′）の上の所定の位置に、ろう付けする面に
１〜８μｍの厚みの金メッキ膜αηを有する半導体レー
ザチップ（２）を載せ、銀ブロック（３）、サブマウン
ト（１′）、半導体レーザチップ（２′）を固定する。As shown in Fig. 2(b), first the silicon submount (1') is placed in a predetermined position on the silver block (3) in a nitrogen atmosphere at 200°C, and then the submount is placed on the silver block (3). A semiconductor laser chip (2) having a gold plating film αη with a thickness of 1 to 8 μm is placed on the surface to be brazed at a predetermined position on the silver block (3), a submount (1′), Fix the semiconductor laser chip (2').

続いて半導体レーザチップ（２′）の上に例えば２０ｙ
の荷重を位置合せを済ませ固定しであるチップ（２’）
、シリコンサブマウント（１′）、銀ブロック（３）に
加えながら、窒素・水素混合ガス雰囲中で温度を４８０
°Ｃに上げ、シリコンサブマウント上にメンキされた金
０１、あるいはシリコンサブマウント上にメッキされた
金αＱおよび半導体レーデチップ（２′）にメッキされ
た金ａηとシリコンサブマウント（１つのシリコンとの
共晶により形成される（［２図（Ｃ）に示すように金・
シリコンろう材（ト）、０１により、銀ブロック（３）
とシリコンサブマウント（１′）およびこのシリコンサ
ブマウント（１′）と半導体レーザチップ（２つを同時
にろう付けする。Next, for example, 20y is placed on the semiconductor laser chip (2').
Chip (2') that has been aligned and fixed the load of
, silicon submount (1'), and silver block (3), the temperature was increased to 480°C in a nitrogen/hydrogen mixed gas atmosphere.
°C and plated gold 01 on the silicon submount, or gold αQ plated on the silicon submount and gold aη plated on the semiconductor radar chip (2'), and the silicon submount (one silicon). Formed by eutectic (as shown in Figure 2 (C), gold
Silver block (3) by silicon brazing filler metal (g), 01
and the silicon submount (1'), and the silicon submount (1') and the semiconductor laser chip (the two are soldered simultaneously).

この昇温時銀ブロック（３）に接したシリコンサブマウ
ント（１′）面には約２０μｍの金・シリコンろう材（
ト）が形成されるが、荷重によりこの金・シリコンろう
材（ト）は銀ブロック（３）上に広がる。同時にシリコ
ンサブマウント（１′）は金・シリコンろう材（至）の
溶けている状態で十数μｍ沈みこみ銀ブロック（３）ト
サプマウン）　（１’）の接着が良好に行なわれる。一
方半導体レーデチツプ（２つとサプマクンｌ−（１’）
のｉｔもサブマウント（１′）のシリコンと半導体レー
ザチップ（２′）にメッキされた金α力が共晶するので
良好に行なわれる。During this temperature rise, approximately 20 μm of gold/silicon brazing material (
However, due to the load, this gold/silicon brazing material (g) spreads over the silver block (3). At the same time, the silicon submount (1') sinks down by more than ten micrometers in the melted state of the gold/silicon brazing material (1'), allowing good adhesion of the silver block (3) (1'). On the other hand, semiconductor radar chips (two and one submachine l-(1')
This process is also carried out well because the silicon of the submount (1') and the gold α plated on the semiconductor laser chip (2') are eutectic.

本発明の一実施例の方法によれば、半導体装置ツ′チッ
プ（２つのろう付される主面に予め金メッキ膜０７）を
設けたので、半導体レーザチップ（２′）のろう材部表
面が酸化されることかなく、したがって半導体レーデチ
ップ（２つをシリコンサブマウント（１′）にこすりな
がらろう付する必要がないので、半導体レーデチップ（
２′）シリコンサブマウント（１′）および銀ブロック
（３）は同時にろう付することができる。すなわち、同
時にろう材が溶けている状態で半導体レーザチップ（１
′）をつかむことは無いので半導体レーザチップ（１つ
の共振器面（６）およびこれに垂直な面（７）にろう材
が付着したりこの面を傷つけたりすることはなくしだが
って半導体レーザの特性が悪くなることは無い。また半
導体レーザチップ（２つ、シリコンサブマウント（１′
）および銀ブロック（３）を同時にろう付したので、ろ
う行中に半導体レーザチップ（２′）が動くという問題
も生じない。According to the method of one embodiment of the present invention, since the semiconductor device chip (the gold plating film 07 is provided in advance on the two main surfaces to be soldered), the surface of the brazing material part of the semiconductor laser chip (2') is The semiconductor Radeh chip (
2') The silicon submount (1') and the silver block (3) can be brazed at the same time. In other words, the semiconductor laser chip (1
'), the semiconductor laser chip (one resonator surface (6) and the surface perpendicular to this (7)) will not be attached to or damaged by the brazing material. The characteristics of the semiconductor laser chip (2) and silicon submount (1') will not deteriorate.
) and the silver block (3) at the same time, there is no problem of the semiconductor laser chip (2') moving during soldering.

なお、本実施例ではブロックとして銀グロックを用いた
が、銀メッキや金メッキを施こした銅ブロックを用いて
もさしつかえない。In this embodiment, a silver Glock was used as the block, but a silver-plated or gold-plated copper block may also be used.

以上説明のように本発明によればシリコンサブマウント
上に半導体レーザ素子を互の金メツキ面が接するように
載せると共に、半導体レーザ素子が載せられたシリコン
サブマウントをこの金メツキ面が接するように金属ブロ
ックに載せ、半導体レーデ素子、シリコンサブマウント
および金属ブロックを同時にろう付けすることができる
ので、半導体レーザ装置の歩留と製造上の作業性が向上
するという優れた効果を有する。As described above, according to the present invention, semiconductor laser devices are mounted on a silicon submount so that their gold-plated surfaces are in contact with each other, and the silicon submount on which the semiconductor laser devices are mounted is mounted so that the gold-plated surfaces are in contact with each other. Since the semiconductor laser element, the silicon submount, and the metal block can be mounted on a metal block and brazed together at the same time, it has an excellent effect of improving the yield and manufacturing workability of the semiconductor laser device.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）〜（Ｃ）は従来の半導体レーザ装置のろう
付方法を示す工程別断面図、第２図（ａ）〜（Ｃ）は本
発明の一実施例のろう付方法を示す工程別断面図である
。 図中、（１′）はシリコンサブマウント、（２′）ハ半
導体レーデチップ、（３）は銀ブロック、０５Ｑｆ９は
シリコンサブマウントに被着された金メッキ膜、α力は
チップに被着された金メッキ膜、（至）ｔよシリコンサ
ブマウントとこれに被着された金の共晶にて形成された
金・シリコンろう材、ａＩはシリコンサプマクン］・と
これに被着された金およびチップに被着された金の共晶
にて形成された金・シリコンろう材である。図中同一符
号は同一または相当部分を示す。 代理人　葛野信− 第１図 第２図 （，２） 第２図 （Ｃ） 手続補正書（自発） 特許庁長官殿 １、事件の表示　　　　特願昭５７−１４１４０７号２
、発明の名称 半導体レーザの製造方法 ３、補正をする者 代表者片由仁へ部 ４、代理人 ５、補正の対象 発明の詳細な説明の欄 ６、補正の内容 （１）明細書をつぎのとおり訂正する。 （２）FIGS. 1(a) to (C) are cross-sectional views showing each step of a conventional brazing method for a semiconductor laser device, and FIGS. 2(a) to (C) are showing a brazing method according to an embodiment of the present invention. It is a sectional view according to process. In the figure, (1') is a silicon submount, (2') is a semiconductor radar chip, (3) is a silver block, 05Qf9 is a gold plating film deposited on the silicon submount, and α force is a gold plating deposited on a chip. film, (to) a silicon submount and a gold-silicon brazing filler metal formed by a gold eutectic deposited on it, aI is a silicon submount] and gold and chips deposited on it. It is a gold-silicon brazing filler metal made of deposited gold eutectic. The same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 1 Figure 2 (, 2) Figure 2 (C) Procedural amendment (spontaneous) Commissioner of the Japan Patent Office 1, Indication of case Japanese Patent Application No. 141407-1988 2
, Title of the invention: Method for manufacturing a semiconductor laser 3, Person making the amendment Representative: Kata Yuhito Department 4, Agent 5, Column 6 for detailed explanation of the invention subject to the amendment, Contents of the amendment (1) The specification as follows. Correct as shown. (2)

Claims (2)

【特許請求の範囲】[Claims] （１）半導体レーザ素子の一方の主面に金メッキを施す
工程と、この半導体レーデ素子が取付られるシリコンサ
ブマクントの両生面にそれぞれ金メッキを施す工程と、
前記シリコンサブマクシト上に前記半導体レーザ素子を
互の金メツキ面が接するように載せると共に、前記半導
体レーザ素子が載せられたシリコンサブマクントをこの
金メツキ面が接するように金属ブロックに載せ、前記半
導体レーザ素子、シリコンサブマクント、及び金属ブロ
ックを同時にろう付する工程を含む半導体レーデ装置の
製造方法。(1) A process of gold plating one main surface of the semiconductor laser element, and a process of gold plating each of the two surfaces of the silicon submacund to which this semiconductor laser element is attached,
placing the semiconductor laser device on the silicon submachine so that their gold-plated surfaces are in contact with each other, and placing the silicon submachine on which the semiconductor laser device is mounted on a metal block so that the gold-plated surfaces are in contact with each other, A method for manufacturing a semiconductor radar device, including the step of simultaneously brazing the semiconductor laser element, silicon submaclant, and metal block. （２）金属ブロックに接する側のシリコンサブマクント
のメッキ厚みを１０〜２０μｍとすることを特徴とする
特許請求の範囲第１項記載の半導体レーデ装置の製造方
法。(2) The method for manufacturing a semiconductor radar device according to claim 1, characterized in that the plating thickness of the silicon submachine on the side in contact with the metal block is 10 to 20 μm.
JP57141407A 1982-08-13 1982-08-13 Manufacture of semiconductor laser Granted JPS5931085A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57141407A JPS5931085A (en) 1982-08-13 1982-08-13 Manufacture of semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57141407A JPS5931085A (en) 1982-08-13 1982-08-13 Manufacture of semiconductor laser

Publications (2)

Publication Number Publication Date
JPS5931085A true JPS5931085A (en) 1984-02-18
JPH0140514B2 JPH0140514B2 (en) 1989-08-29

Family

ID=15291283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57141407A Granted JPS5931085A (en) 1982-08-13 1982-08-13 Manufacture of semiconductor laser

Country Status (1)

Country Link
JP (1) JPS5931085A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6920164B2 (en) * 2000-03-01 2005-07-19 Hamamatsu Photonics K.K. Semiconductor laser device
JP2013004571A (en) * 2011-06-13 2013-01-07 Hamamatsu Photonics Kk Semiconductor laser device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6920164B2 (en) * 2000-03-01 2005-07-19 Hamamatsu Photonics K.K. Semiconductor laser device
JP2013004571A (en) * 2011-06-13 2013-01-07 Hamamatsu Photonics Kk Semiconductor laser device

Also Published As

Publication number Publication date
JPH0140514B2 (en) 1989-08-29

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