JPS5930328A - 論理演算用ユニツトセル - Google Patents
論理演算用ユニツトセルInfo
- Publication number
- JPS5930328A JPS5930328A JP14121482A JP14121482A JPS5930328A JP S5930328 A JPS5930328 A JP S5930328A JP 14121482 A JP14121482 A JP 14121482A JP 14121482 A JP14121482 A JP 14121482A JP S5930328 A JPS5930328 A JP S5930328A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- unit cell
- output
- current
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000004364 calculation method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 241000030538 Thecla Species 0.000 description 2
- 230000001131 transforming effect Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 101100195396 Human cytomegalovirus (strain Merlin) RL11 gene Proteins 0.000 description 1
- 241001674048 Phthiraptera Species 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 210000000436 anus Anatomy 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14121482A JPS5930328A (ja) | 1982-08-14 | 1982-08-14 | 論理演算用ユニツトセル |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14121482A JPS5930328A (ja) | 1982-08-14 | 1982-08-14 | 論理演算用ユニツトセル |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5930328A true JPS5930328A (ja) | 1984-02-17 |
| JPH0357653B2 JPH0357653B2 (cs) | 1991-09-02 |
Family
ID=15286792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14121482A Granted JPS5930328A (ja) | 1982-08-14 | 1982-08-14 | 論理演算用ユニツトセル |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5930328A (cs) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63246920A (ja) * | 1987-04-02 | 1988-10-13 | Agency Of Ind Science & Technol | ジヨゼフソン・デ−タ・セレクタ用単位セル |
| JPH0497423A (ja) * | 1990-08-16 | 1992-03-30 | Nec Ic Microcomput Syst Ltd | 加算器 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5632830A (en) * | 1979-08-27 | 1981-04-02 | Agency Of Ind Science & Technol | Switching circuit making use of josephson effect |
| JPS5799825A (en) * | 1980-12-15 | 1982-06-21 | Agency Of Ind Science & Technol | Josephson logical operation circuit |
-
1982
- 1982-08-14 JP JP14121482A patent/JPS5930328A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5632830A (en) * | 1979-08-27 | 1981-04-02 | Agency Of Ind Science & Technol | Switching circuit making use of josephson effect |
| JPS5799825A (en) * | 1980-12-15 | 1982-06-21 | Agency Of Ind Science & Technol | Josephson logical operation circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63246920A (ja) * | 1987-04-02 | 1988-10-13 | Agency Of Ind Science & Technol | ジヨゼフソン・デ−タ・セレクタ用単位セル |
| JPH0497423A (ja) * | 1990-08-16 | 1992-03-30 | Nec Ic Microcomput Syst Ltd | 加算器 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0357653B2 (cs) | 1991-09-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Radhakrishnan et al. | Low power CMOS pass logic 4-2 compressor for high-speed multiplication | |
| US4363107A (en) | Binary multiplication cell circuit | |
| JPS6014321A (ja) | 多段シフト装置 | |
| JPS62107519A (ja) | 論理回路の設計方法 | |
| EP0849663B1 (en) | Conditional sum adder using pass-transistor logic | |
| JPH01216622A (ja) | 論理回路 | |
| JP3396720B2 (ja) | 部分積生成回路 | |
| JPH035095B2 (cs) | ||
| JPS5930328A (ja) | 論理演算用ユニツトセル | |
| JPH0225537B2 (cs) | ||
| US7325025B2 (en) | Look-ahead carry adder circuit | |
| US5732008A (en) | Low-power high performance adder | |
| Dhanesha et al. | Array-of-arrays architecture for parallel floating point multiplication | |
| CN101799747B (zh) | 一种基于可逆逻辑的算术逻辑单元alu | |
| US4739195A (en) | Mosfet circuit for exclusive control | |
| JPH07117893B2 (ja) | 波及的けた上げ加算器を構成するための回路装置 | |
| US7570081B1 (en) | Multiple-output static logic | |
| Pushpa et al. | Design of shift registers in QCA technology | |
| JPS5834629A (ja) | 論理集積回路 | |
| Lin | Shift switching and novel arithmetic schemes | |
| Amizhdhu et al. | Comparative analysis of 32-bit CSLA based on CMOS and GDI logic | |
| Hänninen et al. | Irreversible bit erasures in binary adders | |
| Ramamoorthy et al. | Fast multiplication cellular arrays for LSI implementation | |
| KR950009683B1 (ko) | 임시합검색 가산기 | |
| JPS63193229A (ja) | 加算回路 |