JPS5930328A - Unit cell for logical operation - Google Patents

Abstract

PURPOSE:To obtain a circuit matched to each kind and each system with the combination of unit cells, by constituting one unit with two OR gates and one AND gate. CONSTITUTION:The unit cell 1 has the 1st OR gate 21 taking In1, In2 as two inputs and the 2nd OR gate 22 taking In3, In4 as two inputs, and the AND gate 4 receiving outputs 31, 32 of both OR gates at each input of the two inputs respectively, and an output of the AND gate 4 is designated as an output OUT of the said unit cell 1. Required number of the unit cells 4 is used and an optional and desired operating system is satisfied depending on the connection of input/output among the cells.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a unit cell which is particularly effective when an arithmetic circuit is assembled using a current injection type closed loop Josephson/switching gater.

A current injection type Josephson switching gate that operates at extremely low temperatures is disclosed in Japanese Patent Application Laid-open No. 56-3283 by the present applicant.
Since its disclosure in No. 0, it has attracted much attention through successive patent applications, conference presentations, publications, etc., and its structure and production principles have become well known.

As a single unit, this gate has high speed, high reliability, ease of design and manufacturing, low power consumption, and is three-terminal, that is, separate from the two terminals for the main current line or circuit current line. It has a number of effects, such as having another control input terminal.

Therefore, due to such excellent properties, there has naturally been a demand for its application to gate logic operation circuits.

In such cases, the most desirable thing is to
A circuit suitable for each system can be obtained simply by combining the same unit cells.

If you do this, you can also do it in the case of integration.

Each unit cell can be manufactured using the same manufacturing process that has been thoroughly examined and perfected, making it possible to reuse manufacturing equipment for masks and other small parts, and the practical effects are enormous.

The first and main object of the present invention is to provide such a unit cell that can be used in other ways.

Although this main purpose is not specific to the logic circuit in which the Josephson element is used, there are certain circuit conditions that are unique to the use of the Josephson element.

Single element logic circuits such as OR gates and AND gates using the above-mentioned type of gates using Josephson elements have already been developed by the applicant, but it is difficult to obtain an overall gain, and the supply voltage is low. The signal itself is low, and therefore the signal that becomes the input to the next stage is weak from a novel perspective.

etc., the fan-in of each elementary logic circuit is 2 or less.

The current situation is that the fan-out must be kept below 3.

Therefore, the second object of the present invention is to provide a unit cell as described above that satisfies this condition so that it is also suitable for Josephson gates.

Yet again. As is already known, the AND gate using the above-mentioned Josephson gate has no external power supply and switches only with an input signal, so it has five inputs and outputs.
＋I can't let go, but on the other hand.

If the OR gate can provide the input/output resistance ratio configuration depending on the power supply, it will improve the stability of one circuit and improve the ei-.

This is most desirable from the viewpoint of manufacturability, integration, etc., and the third object of the present invention is to satisfy these conditions.

Hereinafter, in accordance with the above-mentioned object of the present invention, the process leading to the present invention and the principle of the present invention will be described, and a detailed explanation of a unit cell as an embodiment will be given.

In this explanation, an example of an adder circuit will be used, which can be applied to all other types of arithmetic circuits if discussed. Incidentally, when considering various arithmetic methods and circuits, it is a common practice in this type of technical field to employ adder circuits, not just Josefon elements; conversely, the conclusions obtained regarding adder circuits are as follows. , it is also common knowledge that all of them can be applied to other arithmetic systems.

Therefore, with the main purpose of providing a unit cell with high versatility and reusability, we have also developed the second and third conditions to make it ideal for use as the Josephson gate mentioned above. In summary, the development conditions are as follows.

1) The fan-in of the or gate and and gate used is 2
below.

+V) Do not use an inverter in a series of combinational circuits.

The above iV) is, in the Josephson switching gate,
This is because when introduced into an inverter processing chain, it becomes at least a two-phase clock system, and generally a multi-phase clock system.

This means that a -phase or phasing clock system is desirable if possible.

I reviewed the existing addition method to see if it would satisfy these conditions.

In general, as is well known, there are two main types of existing adders: RCA (Ripple Car).
ryMdar; sequential carry adder), CI, A(
There is a carry lookahead adder).

Here, the summand A, the addend B, the output carry C1, the sum S, and the following are written.

A ” αn・2rL-' + aB I・2rL”
+ -10g, 2i' +-=+a, *z'+a,
*z°= aB"B-1"' ai "'α, α1 as well.

B=h leh road-8...hi...b, b.

Furthermore, the input carry to the i digit in addition is ci-(,
Let kci be the output carry from the i digit, and Sl be the sum of the i digits.

In the above-mentioned RCA, as is well known, K.

It is connected to a two-stage cascade of 1-bit adders and performs operations according to a first-order logical formula.

CL-tXi hi+h@Ci H+Qi Ci,
@111111+111@ (1)zi=at■
hL■'i -1 (2) However, ■ is an exclusive OR, so 1 The inventor has written this well-known formula if)
, (2) & Transform the above conditions 1) to 111)
is satisfied with this, at least as a basic purpose, and furthermore
The idea was to find a formula that would suggest a unit cell configuration that also satisfies the desired conditions.

Under the research, we were able to obtain first-order results.

By transforming the equation (1), the first-order equation (3) can be obtained.

ci = (ai+hi) (α* in + ct-
1) m... (3) In formula (3), first C
Since the product i bi remains, this can be further transformed as follows.

i This formula suggests a very convenient construction. That is,
(4) As can be seen in the part indicated by 1 (,2741) in the formula, the two orgu 14- are used for each of the first and second human power (ct and Q, hi and o), and 7) or. After taking 1, use the AND gate that is the product of both to get fi & -tj, and then similarly use two other OR gates to calculate ai, bi, xi, and C1-1 as each first and second human power. Each or yL+z
By taking ik and ANDing both values yi and xi, the desired ci can be obtained.

The above is a normal carry.

The same applies to zero carry ci.

If you can accomplish this, you will be able to satisfy all conditions 1) to iV) & total.

Next, for the sum of 8 in RCA, use the same process as (2) 7
By transforming the set, the first-order f) (5) equation is obtained.

βL This formula also suggests a very suitable cell configuration.

In other words, two two-person OR gates and the AND of their two outputs? Considering a unit cell consisting of an AND gate, first, by using two of these cells, the part Nαil written together in the above equation (5).

q βLlj') values αL and βL can be obtained, and if we use another cell, we can use the OR gate to obtain the OR of ct and Cj-H, β2 and 4, and then use the AND gate to calculate the product of both. By taking a sum,? i is obtained.

-A'-, and moreover, it is possible to obtain an extremely desirable result in which all conditions 1) to IV) are satisfied.

In the following, I will continue to explain the adoption of the above-mentioned current injection type Josephson gate, which has relatively many single circuit conditions.
Next, CLA as the second additive type will be considered.

CLA is the carry occurrence condition di = αih in one digit
The most significant carry trLk-is to be calculated using i and the one-carry propagation condition O-αi+hif.

Therefore, by rewriting equation (1) as already mentioned, the following equation (6) is obtained.

Cn −dn +arLt rL−1e * e *
m * m a * @ @ 1111 (5) Expand, cn=drL+1n(drb-+ +gn-+ cn-
t )= =drL+gndn-+ -4-an an-1dn-
2-l-tnen-IarL-tdrL-s -1--
---1-grLmrL-+ an-a an-s -
・a s it d+・・・・・・・・・ (7) Equation (7) of 't-, 47°゛11 is f? In addition, the glue is so much better that it is divided into several pit groups and the highest output digit is obtained for each group. The inventor of the present invention searched for a logical formula for each timing stage, and that was sufficient for the above-mentioned RCA. We investigated whether a circuit configuration using only unit cells with two two-man OR gates and one two-man AND gate would be equally promising.

As a result, we were able to achieve satisfactory results in CLA as well.

Here, for the sake of simplicity, we will explain using a 4-bit number as an example.First, in the first timing stage T, the following calculations are performed.

<T1> di-=(ai+o)(hi+o):j=1~4 a
sss (s)ei=(a*-f-o) (2T+o
);i=1~4'' (9)fi=(c
i-1-4) (ai+hi); pin-1~4
... ααgt −(”−1−Az)(ai+bz
); j=1 to 4 e++ss Qll In the second timing stage °r2, primary processing is performed. Hereinafter, the processing of each stage will be listed in sequence, assuming that the timing T indicates the stage number.

<T2> tLz=(at+h2)(”++”+) ”””””
(13tL4 = (αt+be)(αs+'a)
・・・・・・・・・ 0vg−(αz+b2)(”
++A+) ・・・・・・・・・(141x2=(
dt+dr)Caz+ht) −−−−−−−−−(
151”+=(d4+ds) (α, 10 b4) ・
・・”” Q613't=('x+'+) (Lice+Otsu) ・・・・・・・・・ (lη〈T,〉 C,=(Z!+ut) (J!+Co) *** a
a**mm (Is)”t = (y! 10υt) (y
t + et.
・esses ('alc(-(a, +T, )
('gI++r, ) II@661186@11
@ (21) cs-(as+hs) (d3+C2
) @@am-ha...@ (22) 4-(stone+Ts) (es+ct) ・・・・・・・・・
・□□□(14-(J, +u4) (Z4+c2
) l1mma@116@II@Ql)<T,
〉 xi −(fi-4-ci-+) (gi+ci possible)
: *-1 to 4...(25) As above, 1 time T,
Although I am involved up to that point.

As is well known, CLA is more effective as the number of bits increases (actually it is not 4 bits, but more), so this is not a disadvantage, but rather.

If it is configured as a unit cell that is clearly readable from the calculation processing of each stage described above, its general-purpose performance will be extremely large. For example, in the above example, even if the arithmetic method of lA is adopted.

-l knee An adder can be obtained by combining only these unit cells. In other words, the circuit conditions are relatively the same as 1)~
The above-mentioned unit cell can satisfy all the conditions even for current injection type Jose7 non-switching gates, which are common as in IV), and therefore can be used in various arithmetic processing.

This opens the door to the use of Josephson switching gates, which are far more advantageous than other devices in terms of high speed, low power consumption, and high integration.

The above is the principle of the present invention, and FIG. 1 shows a schematic circuit diagram of a unit cell as an embodiment of the present invention in accordance with the principle.

This unit cell/ has a first OR gate 2/ which is powered by two people on Le1+In4, and a second or gate 22 powered by two people on Le5IIN4, and has one or gate output 3/, 31f2. The output of the AND gate is the output Chi of this unit cell.

In this way, one unit cell has an extremely simple structure for a heavy object, but it can satisfy any desired calculation method by using the required number and depending on the input/output connections between each cell. It is very effective. .

In the configuration shown in the first diagram, the devices constituting each OR gate and AND gate may be existing semiconductor devices or optical devices. As mentioned above, one condition is 1.
) to IV) are all satisfied, very desirable results can be obtained by using a current injection type closed Loose-Josephson switching gate.

On the other hand, the OR gate based on this type of Josephson gate,
ANDGATE is its configuration as a single unit.

Since the operation is already known and well-known, once the first illustrated configuration is disclosed, the unit cell/cell can be easily obtained using such existing OR gates and AND gates.

A concrete example of such a case is shown in FIG. Since it is well known, the structure and operation of each gate will be briefly explained. First, the components common to two OR gates: 1/22 and one AND gate are generally four Josephson junction elements J1 to 22. This is the closed loop S included in J4.

The closed loop S has a pair of circuit current terminals pg at two opposing points, with the number of elements being two each for the right branch and the left branch.
, pe are provided, and a control terminal Pc as a third terminal is provided between the pixel elements J, , pe of one branch, in the case of the illustration, the left branch. And also, from the elements J, , J, in the branch with the control terminal,
Elements J, , J4 in the other branch have their critical current values, that is, when operating in an extremely low temperature environment, the potential difference between both ends of the elements transitions from a zero voltage state to a voltage state or resistance state that produces a significant gap voltage. The current value for each operation is set to a large value under design conditions that satisfy each operation.

Or Gate 2/, when it comes to Sco, each two-person power I
l'Ll + IrLt and Inn * 1. , is the input resistance 6/.

-/S-42; A3, after passing through the 4 groups, each closed loop S
is connected to the control terminal PC.

Circuit current terminal P of each closed loop S! I, Pg are power supply V
Each gate is connected to the hot and cold sides of the CC, and between each gate there is a constant current setting resistor for each gate in series with each closed loop.
λ is provided.

Each circuit output 3/, 32 is the hot side P! input terminals uli, 'I:li
is input.

On the other hand, to obtain the required input/output separation, the output resistance RL1
r Input resistance R, 11RIN where the ratio with RLI is a problem
is provided between the control terminal Pc and the ground E or the other circuit current terminal p.

In the AND gate, 1 and 2 positives are dedicated Josephson junction elements Ja, Jh k, respectively.
After passing through the control terminal P of the closed loop S of this gate,
Similarly, dedicated resistors Ret and R
After b k, one circuit current terminal PIK is commonly inputted, and the other end Pg is grounded.

-/6- AND gate output or output of this unit cell/Out
is a pair of circuit current terminals pg of this AND gate,
Pg, and selectively generates an output current to a load RL11 (virtual line) such as an OR gate input of another unit cell (not shown).

To explain the operation assuming that each design condition is satisfied, in each OR gate 2/22, even if only one of the inputs IrL1 or 52: and IrLs or IrL4 has an input current product, the magnitude of the current , the circuit current i! flowing into the closed loop from the power supply VCC! Due to the superposition effect with the left branch component of I.

The element J2 between the ground terminals is brought into a voltage state.

Then, as the left branch component is lost in the closed loop, the single circuit current becomes exclusively the right branch component for elements J, , J, and in addition to this, the input current that is reversely circulated through element J. ic is superimposed, so as mentioned above, no matter how large the critical current value of the element Jl r J4 in this branch is.

A pixel element can no longer remain in the zero voltage state aK and switches from a voltage state to a high impedance state.

Then, the input current ic is exclusively the input resistance Rr1 +R
On the other hand, if the ratio between this resistance and the output resistance is properly determined, the one-circuit current ig predominantly flows through the remaining element Jak to the input resistance RI11Rr.

As a result, the last remaining element J is also removed.

The main component of this large circuit current causes a transition to a voltage state.

When this state is realized, the line portion where the closed loop S is located becomes a high impedance state when viewed from the power supply, so that the circuit current is commutated as output currents isi and i2 to the line where the output load resistors RLI and RL2 are located.

Both people power IrL+ + IrLl: Ias r Ir
Input current IC to L4.

Even in the case of an IC, similar output currents L, Bi and u are obtained, and the OR function is satisfied after all.

Next, I will explain about ANDGATE. First.

7) Suppose that the input current from the previous stage is input to only one of them.

Then, this current flows into the closed loop 5 through the series connection Ja or Jb, but with the magnitude of the current in only one of them, the elements J, , J in the closed loop, especially in the left branch.
, before any significant effect occurs.

Since the series junction Jα or Jb is chosen in a threshold relationship such that it switches to a voltage state, this junction Jα or Jb
b switches, and the current L or i2 flows from the circuit current terminal Py into the closed loop 5 through each dedicated resistor island or Rh, and flows out to the ground E.

Of course, since all the junctions J and WJ4 in the closed loop are in a zero voltage state, the currents i, 2/, i, 2 simply flow out to the ground wire without having any significant effect on them, etc.
Of course, the output 'rtaiO cannot be obtained from the output Out.

After one side input signal input as mentioned above.

If the other input signal comes, the signal on one side is 4JL.
19-, which flows from the closed loop's imaging side, has the same threshold characteristics as the sum gate described above.

Acts as a highly sensitive switch. Also, when both signals are input at the same time, the junctions J, , J in the closed loop switch earlier than the junctions Jα and Jb switch.

, and the current is commutated through the resistors Ra, Rbk to the branches containing the junctions J, , J4. At this time, since it switches at the critical current value of the junction Js + J4, it similarly operates as a highly sensitive switch.

When this state occurs, this terminal pc is no longer in the closed loop, which has a high impedance when viewed from the control terminal pc.
From I2/I2/I2 will no longer flow into each resistance island, after passing through Rh k.

The current becomes the sum again, and the current is commutated toward the circuit current terminal P in the closed loop.

Therefore, in the closed loop S, the established left branch can be said to be isometrically open, and simply connects both terminals Py and P+.
Pixel element J3. Since only J4 is included, the pixel element Jl+J4 can be switched with this value as the sum of both t and Kt and the gate circuit current.

-UO- Thus, the circuit current of this gate can be outputted to the outside as the output current io of one unit cell l.

Thus, the circuit example shown in the second figure completely satisfies the functionality required of the basic configuration shown in the first figure. In addition, various modifications are being made to each gate, so there are various improvements made to each gate as a single unit.

Of course, it can be adopted without any problem.

For further reference, FIG. 3 uses the unit cell shown in FIG. 1 or more specifically shown in FIG.
, output carry ci when building an adder circuit using RCA
(A in the same figure), a combination of the unit cells of the present invention to obtain the zero digits ci (B) necessary in the calculation process, and the sum xi (C) in the same figure.

FIG. 3A is, of course, a logic circuit based on formula (4) already mentioned, and uses two unit cells. Find xi.

Take the or xi of xi and ci-+, the or yik of ai and hi, and the logic of taking the AND in the second cell /
It is calculated using λ and outputs ti.

Note that ai 10 may also be αL 0 αt, which is illustrated as an imaginary line in Figure 1, but of course,
．． As seen in the input of 2, 1, for example, in positive logic hi −
As shown in 1-o, one input may be grounded (S O //).

The ci in Figure 3 (B) has the same cell configuration as in Figure 3 (A), that is, the third and fourth cells are 2, and /A is used to transfer the output of the third cell to the fourth cell. It can be added to the power of one of the or gates, and each signal is all reversed and NarajZt
! 77: I-ru. Signal 1 of both OR gate inputs of the third cell. It is shown that kt□ is added to gates to which H is not added.

As before, you can also add π and anus. This point is the same in the following explanation and in FIG. 4 and subsequent figures.

The sum 9t according to the above-mentioned equation (5) is calculated by inputting each bit value αi, hi, (li?) according to the configuration shown in FIG. 3(C).
, 5 and Figures 3 (A) and (B) ci according to the configuration shown
-+, by ci-1.

It can be determined using three cells lz~/).

In other words, the αt already mentioned in the fifth cell/2, the sixth cell/7
After calculating βt as described above, the seventh cell / The sum Ω can be obtained as the output of L. As mentioned above, the suffix number on the right side of each cell l represents each bit number.

Conversely, when applying the present invention unit cell/f to RCA, the number of cells is 1 bit.

There are seven cells, 1st to 7th cells/: L to 15.

Therefore, if seven z-knit cells /La~/yk are arranged in the column direction and arranged in parallel in the row direction according to the number of bits,
It can be effectively assembled into a well-organized logic array.

FIG. 4 shows an example of an 8-bit configuration, which also shows the spatial layout and layout on the board when integrated circuits are created in such a case.

If one unit cell is formed in advance in 7 rows and 8 columns, each column will have seven cells 4~/S for each bit, and an appropriate wiring pattern will be used to connect each required digit,~ The sum result of S6 and the 23-power carry for the most significant bit to the 9th digit value S are obtained.

In this case, if an 8.times.8 pattern is desired as a forming pattern for each unit cell/.

In addition, since there is no particular need to obtain OK in the most significant bit, cells 4 and 7:t shown by this blank virtual line may not be used, so only the most significant bit can be kept at the required number of cells of five. It's good.

Similarly, by arranging the required number of one unit cell in a matrix with one row and one column as appropriate, a CLA circuit configuration can be adopted only by changing or designing the wiring pattern.

FIG. 5 shows the logic of the 4-bit CLA that can be obtained according to the above-mentioned formulas (8) to (4). .7) This unit cell/... is arranged in the matrix, and connections are made to satisfy each formula. Therefore.

As shown by the virtual line /R in the figure, some redundant cells /R appear, but the manufacturing advantage far outweighs this waste.

12'l - Furthermore, in Figure 1, the rightmost cell row is shown in the opposite direction for convenience of connection diagram.

Each calculation result dL in each timing stage T, ~T, described above, ``+f'+'ILl ''21 ''41
"2 + "41 y21t+2. t't, r
t, , and rt can each be determined for one unit cell. Therefore.

Each of these output cells/... Niha, respectively,
The sign of each output is shown in uppercase letters in the figure. For example, the cell for obtaining the output dif is 6t#i shown as ■.
As described above, the logic SS Ol/ may be the same signal as the other inputs, as seen in the single output of cell D.

As is clear from this figure, if the unit cell of the present invention is used, the CLA method can be expressed by equations (8) to (to), which can be easily assembled into a matrix as an adder circuit according to the CLA method. Since it is possible to construct an aggregate of unit cells of the same configuration, and also completely satisfy conditions 1) to IV), each gate can also be constructed of Joseph non-gates.

High speed, high reliability, small size, and low power consumption systems are highly desirable.

As described in detail above, the present invention completely satisfies the incidental conditions 1) to +V)V as intended, and provides a highly versatile unit cell as the main purpose. In the field of technology, there are many things to contribute to.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an embodiment of a unit cell for logic operations of the present invention, and FIG. 2 is a diagram showing each gate &amp;
A schematic configuration diagram of a configuration using a current-injection closed-loop Josephson switching gate configuration, and Figure 3 shows the configuration to obtain the required signal output for each bit when multiple unit cells are used and applied to RCA. Explanatory diagram. FIG. 4 is a block diagram when RCA is configured by assembling this unit cell matrix, and FIG. 5 is a block diagram when CLA & is configured by assembling this unit cell matrix. In the figure, l is a unit cell of the present invention, 2/, 22 is a two-man OR gate, and lI is a two-man AND gate. Ku ω Q 2

Claims (1)

[Claims] A logic operation unit cell characterized in that first and second two-man-powered OR gates and an ant game 4 which takes an AND of the outputs of the first and second OR gates are constructed as one unit.