JPH0357653B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of constructing an arithmetic circuit device that is effective when constructing an arithmetic circuit using a current injection type closed-loop Josephson switching gate.

A current injection type Josephson switching gate that operates at extremely low temperatures was developed by the present applicant in Japanese Patent Application Laid-Open No.
Since its disclosure in No. 56-32830, it has received much attention through subsequent patent applications, conference presentations, publications, etc., and its structure and operating principle have become well known.

As a single unit, this gate has high speed, high reliability, ease of design and manufacture, low power consumption, and is of a three-terminal type, i.e., separate from the two terminals for the main current line or circuit current line. It has many advantages such as having another control input terminal.

Therefore, because of these excellent features, it is natural that there is a desire to apply this gate to logic operation circuits.

In such cases, the most desirable thing is that no matter what the type of calculation or the various calculation methods, circuits suitable for each type and method can be obtained by simply combining a single or identical unit cells. It is something that can be done.

In this way, even in the case of integration, each unit cell can be manufactured using the same manufacturing process and has been completed with careful consideration, making it possible to reuse manufacturing equipment, including masks and other small parts. Yes, the practical effects will be enormous.

The main object of the present invention is, first of all, to provide such a unit cell that can be used.

However, when using a current injection type Josephson switching element as in the present invention as each active element or elementary logic circuit in a unit cell, the conditions peculiar to this element should be considered as described below. Must be.

Single element logic circuits such as OR gates and AND gates using the above-mentioned gates using Josephson elements have already been developed by the applicant, but it is difficult to obtain an overall gain, and the power supply voltage itself The current situation is that the fan-in of each elemental logic circuit must be kept at 2 or less and the fan-out at 3 or less because the signal input to the next stage is low and the level of the signal input to the next stage is weak.

Therefore, the second object of the present invention is to satisfy this condition in providing the above-mentioned unit cell so that it is also suitable for Josephson gates.

Furthermore, as is already known, the AND gate using the Josephson gate described above does not have an external power supply and switches only with an input signal, so it is not possible to separate the input and output. On the other hand, since input and output can be separated according to the input/output resistance ratio by power supply, it is desirable for the unit cell to be developed to have an OR gate in front of the AND gate. And if you can,
It is most desirable from the viewpoints of circuit stability, designability, manufacturability, integration, etc. if a configuration can be provided that does not require the use of any gates other than the basic gates of the OR gate and AND gate.

A third object of the present invention is to satisfy this condition as well.

Finally, the present invention also provides a method for completing a circuit device that performs a specific logical operation by actually integrating the above-mentioned sum product type unit cell configuration on a single substrate. Rather than changing the arrangement pattern for forming unit cells on a single board each time the desired logical operation changes, we can use the basic method of forming summation-type operations on unit cells in advance, regardless of the desired logical operation. While the structural parts are the same, the arrangement pattern on the board of the plurality of unit cells is also the same, and when each unit cell group performs the desired operation, it is necessary to avoid the fear of creating redundant cells. We aim to provide a device in which only the wiring relationship between unit cells needs to be changed.

In accordance with the above-mentioned purpose of the present invention, the process leading to the present invention and the principles of the present invention will be described below, and a detailed explanation of a unit cell as an example will be given.

In this explanation, an adder circuit will be taken as an example, which can be applied to all other types of arithmetic circuits if discussed. Incidentally, when considering various calculation methods and circuits, the use of adder circuits is a common method in this type of technical field, not just Josephson elements, and conversely, the conclusions obtained regarding adder circuits are It is also common knowledge that this method can be applied to other arithmetic systems.

Therefore, with the main purpose of providing a unit cell with high versatility and reusability, the second and third conditions are taken into account and organized so that it is optimal for using the above-mentioned Zoyosefson gate. , the development conditions are as follows.

() The fan-in of the or gate or and gate used is 2 or less.

() Similarly, fan out is 3 or less.

() The gate before the AND gate is an OR gate.

In addition to this, it is actually desirable to add the following conditions.

() Do not use an inverter in a series of combinational circuits.

The above () is because in Josephson switching gates, when an inverter is introduced into the processing line, it becomes at least a two-phase, generally multi-phase clock system.
This means that a one-phase or single-phase clock system is desirable if possible.

We reviewed existing addition methods to see how they could satisfy these conditions.

In general, as is well known, there are two main types of existing adders: RCA (Ripple
Carry Adder; CLA
(Carry Lookahead Adder)
There is.

Here, the summand A, the addend B, the output carry C, and the sum S are expressed as follows.

A=a _o・2 ^n-1 +a _o-1・2 ^n-2 +…+a _i・2 ^i-1 +…+a ₂・2 ¹
+a ₁・2 ⁰ = a _o a _o-1 …a _i …a ₂ a _1Similarly , B=b _o b _o-1 …b _i b ₂ b _1Furthermore , input carry to the digit of i in addition ci
₋₁ , the output carry from the i digit is ci, and the sum of the i digits is si.

As is well known in the above-mentioned RCA,
One-bit adders are connected in n-stage cascade, and calculations are performed according to the following logical formula.

ci=a _i b _i +b _i c _i-1 +a _i c _i-1 ……(1) si=a _i b _i c _i-1 ……(2) However, is exclusive or. The inventor developed this well-known formula
Transforming (1) and (2), the above conditions () to ()
Based on the idea and research of whether it is possible to obtain a formula that would suggest a unit cell configuration that satisfies these as at least the basic objectives and also satisfies the desirable conditions of (), we were able to obtain the following results. .

By transforming equation (1), the following equation (3) can be obtained.

ci=(ai+bi)(aibi+ci− ₁ )...(3) In equation (3), there remains a part where the product aibi is taken first, so this is further transformed as follows.

This formula suggests a very convenient configuration. That is, as shown in the part indicated by "xi" in equation (4), two OR gates are used to OR the first and second inputs (ai and 0, bi and 0). After that, take the product of both using an AND gate to obtain the value xi,
From now on, each first with two separate or gates, as well
Ors of ai and bi, xi and ci− ₁ as second inputs
If we take yi and zi and AND the two values yi and zi, we will obtain the desired ci.

The above is a normal one carry, but
The same applies to zero carry.

=()+{(+ ₀ )(+ ₀ )−
₁ }
...(4') In other words, regarding the carry ci in RCA, if there is a unit cell configuration in which two two-input ORs are used and the output is ANDed, this same cell can be addressed to four cells for each bit, Just by using it, you can accomplish your purpose and satisfy all conditions () to ().

Next, for the sumi of RCA, use the same process (2)
By transforming the equation, the following equation (5) is obtained.

This formula also suggests a very suitable cell configuration.

In other words, if we consider a unit cell consisting of two two-input OR gates and an AND gate that takes the AND of the two outputs, first, by using two of these cells, the part "αi" also written in the above equation (5) can be , “βi” values αi and βi can be obtained, and if one more cell is used, αi and ci can be obtained using the two input OR gates.
The sum si can be obtained by ORing ₋₁ , βi, and ₋₁ and then multiplying them using an AND gate.

As for RCA, both the output carry ci and ci of each digit and the sum si require only the required number of unit cells consisting of two two-input OR gates and one AND gate that takes the AND of the outputs of both OR gates. It can be covered entirely by
It is possible to obtain the extremely desirable result of satisfying all of ().

In the following, we will continue the explanation with the adoption of the current injection type Josephson gate mentioned above, which has relatively many circuit conditions, but next, we will explain how to use the current injection type Josephson gate as a second adder.
Consider becoming a CLA.

CLA is the condition for carry occurrence in i digit di=aibi
The purpose is to obtain the most significant carry cn at once using the carry propagation condition ei = ai + bi.

Therefore, if we rewrite the above equation (1) using di and ei, we get the following
Equation (6) is obtained.

cn=dn+encn− ₁ …(6) Expand, cn=dn+en(dn− ₁ +en− ₁ cn− ₂ ) 〓 =dn+endn− ₁ +enen− ₁ dn− ₂ +enen− ₁ en− ₂ dn− ₃ + … +enen− ₁ en− ₂ en− ₃ …e ₃ e ₂ d ₁ …(7) Based on equation (7), it is clear from the final term that such a single AND gate with multiple inputs is It is possible.

That is, in reality, numbers A and B with a large number of bits
Because it is impossible to perform parallel simultaneous operations on all bits as a group due to the element configuration,
The bits are divided into several groups and the most significant output carry is obtained for each group.

The present inventor searched for logical formulas for each timing stage, and found that a circuit configuration using only a unit cell with two two-input OR gates and one two-input AND gate, which was sufficient for the above-mentioned RCA, could also be expected. ,investigated.

As a result, we were able to derive results that satisfied this requirement in CLA as well.

For the sake of simplicity, we will use a 4-bit number as an example. First, the first timing stage T ₁
Now perform the following calculation.

<T ₁ > di=(ai+ ₀ )(bi+ ₀ );i=1~4...(8) ei=(+ ₀ )(+ ₀ );i=1~4...(9) fi=(ai+bi )(+); i=1-4...(10) gi=(ai)(+bi); i=1-4...(11) In the second timing stage _T2 , the following processing is performed. Hereinafter, the processing of each stage will be listed in sequence, assuming that the suffix at timing T indicates the stage number.

<T ₂ > u ₂ = (a ₂ + b ₂ ) (a ₁ + b ₁ ) ... (12) u ₄ = (a ₄ + b ₄ ) (a ₃ + b ₃ ) ... (13) v ₂ = ( ₂ + ₂ ) ( ₁ + ₁ ) ... (14) x ₂ = (d ₂ + d ₁ ) (a ₂ + b ₂ ) ... (15) x ₄ = (d ₄ + d ₃ ) (a ₄ + b ₄ ) ... ( 16) y ₂ (e ₂ + e ₁ ) ( ₂ + ₂ ) ... (17) <T ₃ > c ₂ = (x ₂ + u ₂ ) (x ₂ + c ₀ ) ... (18) ₂ = (y ₂ + v ₂ ) (y ₂ + ₀ ) ... (19) <T ₄ > c ₁ = (a ₁ + b ₁ ) (d ₁ + c ₀ ) ... (20) ₁ = ( ₁ + ₁ ) (e ₁ + ₀ ) ...(21) c ₃ = (a ₃ + b ₃ ) (d ₃ + c ₂ ) ... (22) ₃ = ( ₃ + ₃ ) (e ₃ + ₂ ) ... (23) c ₄ = (x ₄ + u ₄ ) (x ₄ + c ₂ ) ... (24) <T ₅ > si = (fi + ci- ₁ ) (gi + _-1 ); i = 1 to 4
...(25) As mentioned above, although it is used until time T ₅ ,
As is well known, in CLA, as the number of bits increases (actually it is not 4 bits, it is more),
Since it is effective, this is not a drawback; on the contrary,
As is clear from the arithmetic processing at each stage described above, being able to use the unit cell that we had in mind has a great effect.

Conversely, if the combination of two two-input OR gates and one two-input AND gate, which is particularly effective as an arithmetic circuit using Josephson switching gates, is configured as a unit cell, its versatility will be greatly increased. . For example, in the above example, no matter which calculation method is adopted, an adder can be obtained by combining only these unit cells. In other words, even for a current injection type Josephson switching gate, which has relatively many circuit conditions () to () mentioned above, the unit cell described above can satisfy all the conditions. Therefore, in various types of arithmetic processing, the use of Josephson switching gates, which are far more advantageous than other devices in terms of high speed, low power consumption, high integration, etc., is opened.

The above is the principle of the present invention, and FIG. 1 shows a schematic circuit diagram of a unit cell 1 as an embodiment of the present invention in accordance with the principle of the present invention.

That is, this unit cell 1 has a first OR gate 21 having two inputs I _o1 and I _o2 and a second OR gate 22 having two inputs I _o3 and I _o4 , and outputs 31 and 32 from both OR gates. It consists of an AND gate 4 which receives one of two inputs, and the output of the AND gate 4 is the output Out of this unit cell.

In this way, although this unit cell has an extremely simple configuration as a single unit, it is highly effective in that it can satisfy any desired calculation method by using the required number of units and determining the input/output connections between each cell. It is what it is.

In particular, the configuration and operation of this type of Josephson gate based on the OR gate and AND gate are already known and well-known, so if the configuration shown in FIG. 1 is disclosed, these existing OR gates,
The unit cell 1 can be easily obtained using an AND gate.

A specific example of such a case is shown in FIG. Since it is well known, to briefly explain the structure and operation of each gate, first, the two OR gates 21,
22 and one AND gate 4 is a closed loop 5 which generally includes four Josephson junction elements J ₁ to _{J 4} .

In the closed loop 5, a pair of circuit current terminals Pg and Pe are provided at two opposing points where the number of elements is two each for the right branch and the left branch, and one branch,
In the illustrated case, a control terminal Pc as a third terminal is provided between both elements J ₁ and J ₂ of the left branch. Also, the elements J 3 , J ₃ in the other branch are more sensitive than the elements J ₁ , J ₂ in the branch with the control terminal.
For _J4 , the critical current value, that is, the current value when transitioning from a zero voltage state with zero potential difference across the device to a voltage state or resistance state that generates a significant gap voltage when operating in a cryogenic environment, is determined by each operation. It is set large under design conditions that satisfy the following.

Regarding the OR gates 21 and 22, two inputs I _o1 and I _o2 and I _o3 and I _o4 are connected to input resistors 61 and 6, respectively.
2; After passing through 63 and 64, each closed loop 5
is connected to the control terminal Pc.

The circuit current terminals Pg and Pe of each closed loop 5 are the power supply
Constant current setting resistors 71 and 72 are connected to the hot and cold sides of Vcc, respectively, and are provided between the two gates in series with each closed loop.

Each circuit output 31, 32 is taken from the hot side Pg, and is inputted to each input terminal 41i, 42i of an AND gate 4, which will be described later, via load resistors R _L1 , R _L2 .

On the other hand, the ratio of the input resistances R _I1 and R _I2 to the output resistances R _L1 and R _L2 becomes a problem in obtaining the required input/output separation capability.
is the control terminal Pc and the ground E or the other circuit current terminal
It is established between Pe.

In AND gate 4, both inputs 41i, 42
i is a dedicated Josephson junction element Ja, Jb, respectively
After that, it is commonly connected to the control terminal Pc of the closed loop 5 of this gate, and similarly, each dedicated resistor
After passing through Ra and Rb, one circuit current terminal is commonly used.
It is input to Pg, and the other end Pe is grounded.

The AND gate output or the output Out of this unit cell 1 is obtained between the pair of circuit current terminals Pg and Pe of this AND gate, and the load R _L0 such as the OR gate input of another unit cell (not shown) is obtained.
(phantom line) selectively produces an output current.

To explain the operation assuming that each design condition is satisfied, in each OR gate 21, 22, even if there is an input current ic only to one of the inputs I _o1 or I _o2 ; and I _o3 or I _o4 , the current Due to the superposition effect with the left branch component of the circuit current ig flowing into the closed loop from the power supply Vcc, the element J ₂ located between the ground terminals transitions to the voltage state. Then, the circuit current ig becomes a right branch component exclusively for elements J ₃ and J ₄ due to the loss of the left branch component in the closed loop, and in addition to this, the input current ic which is in the opposite direction via element J ₁ As mentioned above, no matter how large the critical current value of elements J ₃ and J ₄ in this branch is, both elements can no longer remain in the zero voltage state and the voltage state changes to high voltage. Switch to impedance state.

Then, the input current IC depends exclusively on the input resistances R _I1 and R _I2
On the other hand, if the ratio between this resistance and the output resistance is appropriately determined, the circuit current ig will predominantly rush to the input resistances R _I1 and R _I2 via the remaining element J ₁ .

As a result, the last remaining element _J1 also becomes
The main component of this large circuit current ig causes a transition to a voltage state.

When this state occurs, the line portion where the closed loop 5 is located becomes a high impedance state when viewed from the power supply, so the circuit current is commutated to the line with the output load resistances R _L1 and R _L2 as output currents i21 and i22. .

Both inputs I _o1 and I _o2 ; input currents ic and ic for both I _o3 and I _o4
, the same output currents i21, i2
2 is obtained, and the OR function is satisfied after all.

Next, AND gate 4 will be explained. First,
Assume that the input current i21 or i22 from the previous stage is input to only one of the inputs 41i and 42i.

Then, this current flows into the closed loop 5 through the series junction Ja or Jb, but the magnitude of the current in only one of them causes a significant effect on the elements J ₁ and J ₂ in the closed loop, especially in the left branch. Having previously chosen a threshold relationship such that the series junction Ja or Jb switches to a voltage state, this junction Ja or Jb switches and the current i21 or i22 flows through the respective dedicated resistor Ra or Rb. The circuit current flows into the closed loop 5 from the circuit current terminal Pg and flows out to the ground E.

Of course, since all the junctions J ₁ to _{J 4} in the closed loop are in a zero voltage state, these currents i21 and i22 simply flow into the ground wire without having any significant effect on them. Therefore, the output current io cannot be obtained from the output Out.

After one side input signal input as mentioned above,
If the other input signal is coming, the signal on one side is
Since it flows from the power supply side of the 4JL closed loop,
It has the same threshold characteristics as the sum gate described above, and works as a highly sensitive switch. Also, when both signals are input at the same time, the junctions J ₁ and J ₂ in the closed loop are switched on earlier than the junctions Ja and Jb are switched on, and the current flows through the resistors Ra and Rb to the junction J ₃ ，
Translocate to the branch containing J ₄ . At this time, the junction J ₃ ,
Since it switches at the critical current value of _J4 , it also operates as a highly sensitive switch.

When this state occurs, both currents i21 and i22 will no longer flow from this terminal Pc into the closed loop, which is at high impedance when viewed from the control terminal Pc, and will flow through the respective resistors Ra and Rb again. This becomes a sum current and commutates toward the circuit current terminal Pg in the closed loop.

Therefore, in closed loop 5, the left branch can be equivalently said to be open, and simply connects both terminals.
Since both elements J ₃ and J ₄ are connected in series between Pg and Pe, the sum of these two currents is set as the circuit current ig of this gate, and both elements J ₃ and J ₄ are switched at this value. You will be able to do so.

Thus, the circuit current ig of the gate 4 can be outputted to the outside as the output current io of the unit cell 1.

In this way, the circuit example shown in the second diagram is completely
It satisfies the functions required for the illustrated basic configuration.
Incidentally, since various modifications are being made to each gate, it is of course possible to incorporate such various improvements as a single unit without any problem.

For further reference, FIG. 3 shows the output carry ci (A ), a zero carry required in the calculation process (B in the same figure), and a sum si (C in the same figure).

FIG. 3A is, of course, a logical circuit of the above-mentioned formula (4), and uses two of the present unit cells 1.
First, find xi in formula (4) in the first cell 1 ⁱ _a , and use this xi
The OR zi between and ci− ₁ and the OR yi between ai and bi are taken, and the logic for ANDing them is determined in the second cell 1 ⁱ _b and ci is output.

Note that ai + ₀ may also be ai + ai, which is illustrated by a virtual line in the figure, but of course, as shown in the input of the second OR gate 22, for example, as shown by bi + ₀ in positive logic, One input may be set to "0" as shown by grounding.

The cell configuration in FIG. 3B is exactly the same as that in FIG. 3A, that is, the third and fourth cells 1 ⁱ _c and 1 ⁱ _d are used, and the output of the third cell is connected to one OR gate of the fourth cell. It can be added to one input of the , and each signal is all inverted. It is shown that "0" is added to the gates to which the signals of both OR gate inputs of the third cell are not added, but as before,
You may also add , respectively. This point is the same in the following explanation and in FIG. 4 and subsequent figures.

The sum si according to equation (5) described above can be calculated by dividing the sum si into three cells using the configuration shown in _{FIG .} It can be found by 1 ⁱ _e and 1 ⁱ _g .

In other words, the αi already mentioned in the fifth cell 1 ⁱ _e is
After calculating βi as described above in ⁱ _f , input carry ci- ₁ according to the cell configuration in Fig. 3A, as in Fig. 3B.
Zero carry by constructing - 7th cell with the help of ₁
The sum si can be obtained as the output of 1 ⁱ _g . In the above description, the suffix i on the right side of each cell 1 represents each bit number.

Conversely, when the unit cell 1 of the present invention is applied to RCA, the number of cells per bit is seven, from _the first to _seventh cells ^1ia , ^1ig .

Therefore, by arranging seven unit cells 1 ⁱ _a , 1 ⁱ _g in the column direction and arranging them in parallel in the row direction according to the number of bits, a well-ordered logic array can be effectively assembled in terms of integration.

FIG. 4 shows an example of an 8-bit configuration that also shows the spatial arrangement and the arrangement on the board when integrated circuits are formed in such a case.

If the unit cells 1 are formed in advance in 7 rows and 8 columns, seven cells 1 ⁱ _a and 1 ⁱ _g in each column will be used for each bit, and each required digit s will be connected by an appropriate wiring pattern. The sum result of ₁ to _s3 and the most significant bit output carry to the ninth digit value _s9 are obtained.

In this case, an 8x8 pattern is used for each unit cell.
. . . If it is desired as a formation pattern, one line becomes redundant, but it is of course possible to do so. Also, in the most significant bit, there is no particular need to obtain ₈ , so cell 1 ⁸ _c , shown by the imaginary line for this purpose, is
^18d may not be used, and therefore only the most significant bit can be kept to the required number _of cells of five.

Similarly, by arranging the required number of unit cells in a matrix with an appropriate number of rows and columns, it is also possible to adopt a CLA circuit configuration by simply changing or designing the wiring pattern. In other words, using the summation type unit cell disclosed by the present invention, and
According to the process of creating multiple identical unit cells with exactly the same layout pattern on a single board, simply changing the wiring relationship between the unit cells can
A desired logical operation can be selectively executed among a plurality of possible logical operations. It goes without saying that such sharing of device fabrication patterns is extremely advantageous when constructing this type of integrated circuit as a tangible product. The embodiment shown in FIG. 5, which will be described below, proves this.

Figure 5 shows a 4-bit CLA logic array for obtaining results (24) and (25) in accordance with equations (8) to (25) already mentioned. 8×
The unit cells 1... are arranged in a matrix of 6, and wires are connected so as to satisfy each formula. Therefore, as shown by the imaginary line 1R in the figure, there are some redundant cells 1R, but this waste is far outweighed by the manufacturing advantage.

Furthermore, in the figure, the rightmost cell column is shown in the opposite direction for convenience of connection diagram.

Each calculation result di, ei, fi, gi, u ₂ , u ₄ , x 2 , x _{4 ,} y ₂ , in each timing stage T ₁ to T ₅ described above
Each of v ₂ , ci, and si can be determined for one unit cell. Therefore, in the cell 1 for obtaining each of these outputs, the code of each output is shown in uppercase letters in the figure. For example, the cell for obtaining the output di is indicated as Di. As described above, as seen in one input of the cell _D1 , the logic "0" may be the same signal as the other inputs.

As is clear from this figure, if the unit cell of the present invention is used, the CLA method can be expressed by the above-mentioned equations (8) to (25), and the same configuration can be easily assembled into a matrix as an adder circuit using the CLA method. It is possible to construct an aggregate of unit cells, and the conditions () ~
Since () can be obtained in a form that completely satisfies, each gate can be constructed with Josephson gates, making it extremely promising as a high-speed, highly reliable, miniature, and low-power system.

As described in detail above, the present invention, as intended, fully satisfies the incidental conditions () to (), and discloses a highly versatile unit cell as the main purpose, and provides logic using this unit cell. It provides a method for constructing an arithmetic circuit device, and has a particularly significant contribution to the field of Josephson technology.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of one embodiment of a unit cell for logic operations according to the present invention, and FIG. 2 is a diagram showing a case where each gate of the unit cell shown in FIG. 1 is configured using a current injection type closed-loop Josephson switching gate configuration. A schematic configuration diagram. Figure 3 is an explanatory diagram of the configuration for obtaining the necessary signal output for each bit when multiple unit cells of this type are used for RCA. Figure 4 is a diagram of the configuration of RCA by assembling these unit cells into a matrix. Figure 5 is a diagram showing the configuration of a CLA by assembling this unit cell into a matrix.
It is. In the figure, 1 is a unit cell of the present invention, 21 and 22 are two-input OR gates, and 4 is a two-input AND gate.

Claims (1)

[Claims] 1. First and second current injection type two-input Josephson OR gates having an input/output separation function, and a single current injection type two-input Josephson OR gate having no input/output separation function. A sum product type consisting only of an input Josephson AND gate, and both outputs of the first and second Josephson OR gates are connected to one of the two inputs of the Josephson AND gate. Using a plurality of logic operation unit cells; regardless of the target logic operation expression, all of the plurality of mutually identical sum-product logic operation unit cells are placed on a single board in the same manner and according to a predetermined arrangement pattern. After formation; among the plurality of unit cells for summation-type logic operations that are all the same, the input and output of at least some cells are controlled according to the target logic operation expression, while allowing the generation of redundant cells. A method of constructing a Josephson logical operation circuit device, characterized by: wiring and connecting;