JPH01256219A - Logic circuit - Google Patents

Abstract

PURPOSE:To constitute the logic circuit using either a positive logic or a negative only by connecting basic cells of a logic cell in multi-stage, arranging a normal logic gate not including any transfer gate TG to the fine stage as the logic element and obtaining a desired logic output from the normal logic gate. CONSTITUTION:Two stages or over of the basic cells 1 are connected, an output signal F of the pre-stage or its inverting signal F is used at least as one input signal of 1st and 2nd transfer gates TG1, TG2 of the next stage, and the normal logic gate 2 not including any transfer gate at the final stage, that is, the inverter, a simple gate such as a multi-input NOR or an inverter, a simple gate such as a multi-input NAND and a multi-input logic gate such as a composite gate is arranged as one element constituting the desired logic and its output is used as the desired logic output. Thus, the transfer gate is used to apply desired logical operation.

Description

[Detailed Description of the Invention] [Summary] Regarding a logic circuit using a transfer gate, an object of the present invention is to make it possible to configure a logic circuit with only either positive logic or negative logic using TG, a first transfer gate to which a first input signal is input; and a second transfer gate to which a second input signal is input; A group of circuits in which the outputs obtained from the first and second transfer gates are wired-OR connected with one of the transfer gate and the second transfer gate turned on and the other turned off is used as a basic cell. , the basic cells are connected in multiple stages so that the output signal of the basic cell is used as an input signal to at least one of the first and second transfer gates of other basic cells, and the final stage does not include a transfer gate. Logic gates are arranged as logic elements, and a desired logic output is obtained from the normal logic gates.

[Industrial Application Field] The present invention relates to a logic circuit using a transfer gate.

[Conventional technology]

Conventional logic circuits use field effect transistors (FETs) such as MO3 type transistors, but FETs
A transfer gate (or transmission gate, hereafter abbreviated as TG), which utilizes the bidirectional characteristics of the MOS transistor (same electrical characteristics even if the source and drain electrodes are reversed), is generally used as a selector or flip-flop. It is used only as a logic circuit, and is not normally used as a general logic circuit.

The reason why TG is difficult to use in general logic circuits is that (a) T
When switching the signal path using G2&I1 or more, if the input timing to the TG gate terminal is shifted, malfunction may occur.

(b) In response to a certain combination of signal inputs, the internal nodes of the circuit become floating (high impedance), which may cause a steady current to flow in a CMO3 circuit or the like. Furthermore, signals that have passed through the TG may collide with each other.

(c) For the signal passing through the TG when the TG is on, T
Since the element impedance of G has a resistance component, it is no longer possible to determine the signal delay by considering only the load capacitance, as is normally the case when inputting a signal to the gate.

Therefore, the method of determining gate delay becomes complicated.

This is because there are reasons like this.

There are examples of logic circuits using TGs that solve the above problems, but in that case, unlike normal logic circuits, positive logic and negative logic must be used alternately for each stage. This made circuit design and circuit analysis extremely difficult.

[Problem to be solved by the invention]

If TG can be used effectively, it is possible to construct a desired logic circuit at higher speed than normal logic circuits and with a smaller number of elements. Generally not used in logic circuits.

It is an object of the present invention to use TG to configure a logic circuit with only either positive logic or negative logic.

[Means to solve the problem]

Hereinafter, with reference to FIG. 1, an example will be explained in which a positive logic is used in a CMO3 logic circuit, but a circuit having a similar function can also be constructed using a negative logic.

FIG. 1 is a diagram showing the basic configuration of the logic cell of the present invention. As seen in the figure, the logic cell has basic cells 1 connected in multiple stages, and the final stage is a normal logic gate that does not include a transfer gate TG. 2 is arranged as a logic element, and the structure is such that a desired logic output can be obtained from this ordinary logic gate 2.

This basic cell 1 has a first transfer gate TGI to which the first human power signal In+ is input, and a second transfer gate TG2 to which the second human power signal 1nz is input.
and a third input signal In, which is an inverted signal In.

turns one on and the other off. The switching means SW is an inverter that inverts the third input signal 1n3.

The first and second transfer gates TG1, TG
The outputs out1 and out2 of the basic cell 1 were wired-OR connected, and one of them was configured to be output as the output signal F of the basic cell 1.

In the present invention, the basic cells 1 are connected in two or more stages, and the output signal F of the previous stage or its inverted signal F is transmitted to the first and second stages of the next stage.
transfer gate TGI.

At least one of T G 2 is a human input signal, and furthermore, it is a normal logic gate 2 which does not include a transfer gate in the final stage. That is, an inverter or a large amount of power N.

R2 A multi-input logic gate such as a simple gate composite gate such as a large power NAND is arranged as one of the elements for configuring the desired logic, and the output is configured to be the desired logic output. be.

In the present invention, with the above configuration, a logic cell that performs a desired logical operation is configured using a transfer gate.

Note that the present invention also includes a circuit having a configuration obtained by performing equal replacement from the circuit configured as described above.

Note that when using an inverted signal of the output F of the basic cell 1, the output F may be outputted via the illustrated inverter I.

[For production]

The present invention solves the problem by using the TG as follows.

First, the basic configuration of a basic cell l using TG is shown in FIG. 1, which consists of two sets of transfer gates TGI and T.
G2 to one of its source/drain terminals 3.4 (first
In the figure, 4) is connected as an output terminal with a wired-OR connection,
The terminals on the opposite side (3 in the figure) are respectively signal input terminals, and the third human power signal Ins is input to one of the control terminals 5 and 6 (6 in the figure) of the TG, and the third human power signal Ins is input to the other control terminal. TGI by inputting an inverted signal 1nt.

The deviation in the input timing to the control terminal 5.6 of TG2 results in a delay of at most one inverter stage, and since this value is smaller than the delay of other logic gates, problem (a) is resolved.

In addition, since only one of the inputs to the control terminals 5 and 6 of TG1 and TG2 is always on, collisions between different signals are avoided, and the input node itself to the basic cell 1 is Unless the impedance becomes high, the impedance does not become high within the basic cell 1. Therefore, the problem [exist]) is solved.

Regarding problem (C), the output signal of the final stage in Fig. 1 can be converted to a normal logic gate (inverter, simple gate such as large-power NOR, large-power NAND, etc.) that does not use TG, or a compound gate.
This can be solved by making the entire circuit including the normal logic gate 2 a logic cell, ie, a logic circuit unit, which configures the desired logic.

In a logic cell configured in this manner, the signal delay can be easily calculated, and its value can be determined only by the magnitude of the capacitive load connected to the output node of the logic cell.

In methods of designing circuits using logic cells, such as the gate array and standard cell methods, circuits that are various combinations of the above logic cells and normal logic gates are treated as one logic circuit, and their logic, delay data, and layout are - It is possible to register data, etc. and design an LSI that combines them as necessary.

〔Example〕

The logic circuit according to the present invention includes a multi-input composite logic cell configured by directly connecting two or more stages of the above-mentioned basic cells 1, and embodiments thereof will be described below with reference to the drawings.

FIG. 2 is a diagram showing a first embodiment of the present invention, in which the basic cell 1 is a transfer gate 'TGI.

Consists of TG2 and inverter ■2, its output F
2 as the transfer gate TG3 of the next basic cell l'
Another input signal C is inputted to the input terminal of the transfer gate TG4, and another input signal C is used as a control signal for the subsequent basic cell 1', and the output Fl is passed through the inverter 11 to generate its inverted output Y. This is what I did.

The output Y of the multi-input logic circuit of this embodiment consists of five input signals A1, A2 . For B, C, and D, Y=τ・D+(AI
・B+A2・T)・D −■ It is expressed by the logical formula.

As is clear from FIG. 2 and Equation 0 above, the configuration of this embodiment is such that in a logic circuit using a conventional transfer gate (hereinafter abbreviated as TG), the logic is completed immediately before the inverter 11 at the final stage. , the inverter 11 is used as one of the elements for configuring logic, unlike the case where the inverter 11 is used simply for shaping the signal waveform. Therefore, the logic is not inverted between positive and negative by the inverter 11 at the final stage, and therefore, it is possible to maintain consistency with only one of the positive logic and negative logic without mixing them.

In the circuit shown in Figure 2 above, the output F of the basic cell 1 in the previous stage
2 is the input of the subsequent transfer gate TG4, and the input signal C is the input of the transfer gate TG3, then the output Y is Y- and D+(-λ-'B + A2 T)
・Hair---■.

In addition, in the same figure, if Al=A, A2-λ-, then Y=
(A-B+A-B) ・D+・D ------
−−■.

Signal inputs A1, A2 . C is at least 1
One is an independent signal of logic 0 and 1, and the remaining signals may be inverted signals of other signals.

Furthermore, the input signal C may be an inverted signal of the output F2 of the basic cell 1 at the previous stage. In this case, the output Y is Y=(Al・B
+A2・T)・−b− +(AI・B+)11・T)・D ・−・−■
becomes.

Furthermore, when Al=A and A2=τ, the formula ■ becomes Y= (A
-B)+A-■)・100+(A-B+A-B)・D---10, resulting in a three-man power ENOR circuit of A, B, and D.

When Al=-1 and A2=A, a three-man power EOR circuit is similarly constructed.

The output signal YC formula when F2 is input to Te3 and C is input to Te3 in Fig. 2] is as follows: If C is the inverted output of F2, then Y=(AI・B+A2・T)・D +( AI ・B+A2 ・T)・100 −・−〇.

Furthermore, if you input AI=A, A2-τ, this output becomes Y= (A-B+A-B) ・D + (A-B+A-B) ・D −−−−−−1■, A three-person EOR circuit of A, B, and D is configured, and A1=
If A, A2=A, a three-man power ENOR circuit is similarly constructed.

FIG. 3 is a diagram showing a second embodiment of the present invention, in which two sets of first-stage basic cells are prepared, and their outputs F2. F3 is connected to the two input terminals of the basic cell in the next stage and combined with another input C, and the output of the basic cell in the next stage is inverted by the inverter 11 to obtain the output Y. A variety of circuits similar to those described in the illustrated circuit can be constructed.

The output Y of the circuit in Fig. 3 is Y= (AI-B+A2-B) ・C・ (T1 "・
B+1 "Σ・T)・is expressed as -----・-・■.

In the circuit shown in the figure, instead of F2, a signal F2 obtained by inverting F2 using an inverter is input to Te3.

Of course, a configuration in which F3 is input to Te3 instead of F3 is also conceivable.

FIG. 4 is a diagram showing a third embodiment of the present invention. In FIG. 3, A1→, A2→C, B-+A.

In this configuration, E→A and C→B are replaced with DI−+C, D2→, and in this case, the output Y becomes Y=A eB eC---10, which shows that it is a three-man power EOR circuit.

Similarly, an ENOR circuit can also be configured.

The three-man power EOR circuit is used as a circuit that outputs a sum signal of a binary addition circuit from three inputs: an addend, an augend, and a carry output from the lower bits.

FIG. 5 is a diagram showing a fourth embodiment of the present invention. In the circuit of FIG. 3, Al→0. A2→τ.

B-+C, Dl→A, D2→1. E−+C, C−+B, Y=A −B+B −C+C−A −−−−[
An output of [stock] is obtained. This is a carry circuit for the adder circuit, and in combination with the circuit shown in FIG. 4, a 1-bit full adder circuit can be constructed.

Note that T G using a complementary circuit such as CMO3FET
In the configuration shown in FIG. 6, the N-channel element of the TG can generally be omitted when the input is always 1', and the P-channel element of the TG can be omitted when the input is always 0. The circuit of the fifth embodiment of the present invention can be used as a circuit having exactly the same function as the circuit of the fourth embodiment shown in FIG. It also includes.

FIG. 7 is a diagram showing a sixth embodiment of the present invention, which is an example of a four-person EOR circuit in which three or more of the basic cells l shown in FIG. 1 are connected in series and output is obtained through a gate of an inverter or the like. .

A four-person power ENOR circuit can also be realized in the same manner.

FIG. 8 is a diagram showing a seventh embodiment of the present invention, in which a two-man NAND circuit is used as the normal logic gate 2 in FIG. 1.

In this way, a more complex logic circuit can be constructed by combining a multi-input simple gate or composite gate with a TG circuit.

As described above, the present invention converts the basic cell 1 in FIG.
A multi-input TG using a TG, which is characterized in that the horns are connected in series and then entered into a normal logic gate such as an inverter or a multi-input simple gate composite gate, and the inverted output is used as the desired logic output. The present invention provides a method for configuring a complex logic circuit. In addition, in the present invention, a digital binary logic circuit can be constructed using only either positive logic or negative logic, and there is no need to mix both when constructing a circuit as in the conventional example.

Therefore, according to the present invention, the circuit configuration and the node potential of the circuit correspond one-to-one, compared to the case where both are used in combination, making circuit design and logic design easier.

As mentioned above, the reason why positive logic and negative logic had to be mixed in the conventional configuration is that the final stage inverter is not used as a logic element to configure the desired logic.
This is because it was provided simply because it was necessary to shape the signal waveform. By constructing a logic circuit using a circuit that does not use an inverter and placing an inverter in the final stage, the logic is reversed, making it impossible to configure a consistent circuit with positive or negative logic, and changing the logic from input to output. The logic on the way is,
As a mixture of positive and negative signals, it was necessary to finally obtain the desired logic output.

In the present invention, which solves this problem, the delay due to the multi-stage series TG is kept within a predictable range, and the CMO
In 3 circuits, etc., the propagation delay of the circuit can be calculated using only the load capacitance, making timing design easier, and the circuit operation becomes faster compared to the conventional example in which the output is obtained by connecting two stages of inverters in series. It can be designed to

Although each of the above embodiments has been described as an example in which the circuit is configured using positive logic, it goes without saying that a circuit configuration using negative logic is also possible using the present invention.

In addition, although the specific example has been described assuming a complementary circuit, the logic circuit according to the present invention does not necessarily have to be a complementary circuit, and can be equivalently configured using an element 1 having a single polarity, for example, an nMO3 logic circuit. It also includes circuits that are

[Effects of the Invention] As described above, according to the present invention, the number of elements can be reduced, the speed of the circuit can be increased, and power consumption can be reduced by using a single circuit or in combination with other similar circuits. Also, compared to the conventional configuration that mixes positive and negative logic, it simplifies circuit design and reduces design errors.

Advantages such as the ability to realize a more complex circuit configuration can be obtained.

This results in an LS with higher functionality, higher speed, and lower power consumption than before.
I can be realized using a conventional design method.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the configuration of the present invention, Fig. 2 is an explanatory diagram of the first embodiment of the invention, Fig. 3 is an explanatory diagram of the second embodiment of the invention, and Fig. 4 is an explanatory diagram of the third embodiment of the invention. FIG. 5 is an explanatory diagram of the fourth embodiment of the present invention, FIG. 6 is an explanatory diagram of the fifth embodiment of the present invention, and FIG. 7 is an explanatory diagram of the sixth embodiment of the present invention.
FIG. 8 is an explanatory diagram of a seventh embodiment of the present invention. In the figure, 1 and Bi are basic cells, 2 is a normal logic gate, 3 and 4 are either source or drain electrodes, 5 and 6 are control circuits, TG is a transfer gate, SW is a switching means, In+~Int, and A
, B, C, D, E. G is an input signal, F is an output signal of a basic cell, Y is an output signal of a logic cell, OuL+ and Quit are output signals of a basic cell, 1. If~+7. And If'~I 坏发 4 ri 2's r ug is the 3rd figure of Chokoku invention Oha Daishin example is -m lj chi 3 g, ql° t + 4: 4 column rj: 9. El
i Non-explosion θJ4 5th A large planer example α clear figure Fig. 6 Fig. Non-explosion τi modification example Tt eH figure Fig. 7

Claims (1)

[Claims] A first transfer gate (TG1) to which a first input signal (In_1) is input, and a second transfer gate (TG2) to which a second input signal (In_2) is input. one of the first transfer gate (TG1) and the second transfer gate (TG2) is turned on and the other is turned off by a third input signal (In_3) and its inverted signal;
The first and second transfer gates (TG1, T
A basic cell (1) is a group of circuits in which the outputs (out1, out2) obtained from G2) are wired-OR connected, and the output signal (F) of this basic cell (1) is connected to another basic cell (1).
) of the first and second transfer gates (TG1,
The basic cells (1) are connected in multiple stages as an input signal to at least one of the TG2), and a normal logic gate (2) not including a transfer gate is arranged as a logic element in the final stage, and the normal logic gate (2) A logic circuit comprising a logic cell configured to obtain a desired logic output.