JPS59139446A - Adding circuit - Google Patents

Abstract

PURPOSE:To shorten considerably the carry signal transmission route of a critical path, by attaining a full adder which has a double addition speed of a conventional full adder with simple circuit constitution. CONSTITUTION:Three input signals ai, bi, and ci to be added in the full adder and signals -ai, -bi, and -ci attained by inverting them by inverters are inputted to two logical gates (1a and 2a), and a sum output Si is attained from these gates. In the full adder of a type 1, a carry output signal -ci+1 having the opposite polarity is attained from two logical gates to which signals ai, bi, and ci are inputted. In the full adder of a type 2, a carry output signal ci+1 having the positive polarity is attained from two logical gates to which signals -ai, -bi, and -ci are inputted. Plural pairs of these full adders are provided, and they are arranged alternately, thereby realizing the high-speed transmission of the carry signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an adder circuit for adding two multi-digit numbers;
In particular, it relates to an adder circuit that is optimally constructed using CMOS transistors (complementary insulated gate field effect transistors).

Conventional configuration and its problems The conventional adder circuit is the first one. Shown in Figure 2.

FIG. 1 shows a known full adder, in which 1 and 2 are EXOR (exclusive OR) gates, 3, 4, and 5 are IVAND gates, and the first digit is the addition number Ai1, the i-th digit is Input the th augend Bi and the carry signal Ci to the i-th digit,
Sum S i of 1st digit, carry signal Ci to i-th + 1st digit
This function has the function of outputting +1. Therefore, SL and Ci
+1 is represented by 5i=Ai■Bi■C1 C1+1 =AiBi+C1 (At■Bi). FIG. 2 shows an adder circuit using the full adder of FIG. 1 in a case where addition aA1 and addend B both have 4 pits.

Reference numerals 10 to 13 are full adders shown in FIG. 1, and gates 1 to 5 constituting 1o are exactly the same as the gates with the same numbers shown in FIG.

In other words, the circuit in diagram g2 is a ripple carry type adder circuit, which has an addend (A4A3A2A1) and an augend (84
It has a function of inputting the 4-bit sum (S4S3S2S1) and the carry signal C6 from the 4th digit by inputting the 4-bit sum (S4S3S2S1) and the carry signal C1 to the 1st digit.

If the number of additions At, the number of augends Bi, and the carry signal C1 are input at the same time, in order to obtain the sum S1, an EXOR gate (
EXOf
't The delay time for one stage of gate and the second stage of NAND gate are required, and when the EXoR gate is configured with a 0MO8) run resistor, it can be regarded as the delay time equivalent to two stages of NAND or NOR gate, so the sum S1 is the delay time of 2 stages of NAND gate. The final carry constant C6 is obtained by waiting a delay time of 10 gate stages. Generally, in the case of addition of n-bit numbers, a delay time equivalent to 2n+2 stages of gates is required to obtain the carry signal Cn+1, which is the critical path.

OBJECTS OF THE INVENTION The present invention aims to provide an arithmetic circuit that can significantly shorten the long critical path of conventional adder circuits and perform high-speed addition.

Structure of the Invention The present invention has a full adder as a component thereof.
A sum output St is obtained from two logic gates that receive six input signals: three input signals ai, bi, ci and signals ai, bi, ci which are inverted by an inverter, while at, bi , Of, and a type 1 full adder which obtains a carry output signal Ci+1 of opposite polarity from two logic gates whose inputs are at, bi.

By providing a plurality of two types of full adders of type 2 that obtain a positive carry output signal C1+1 from two logic gates that input ci and arranging them alternately, carry This enables high-speed signal propagation.

Description of examples The present invention will be described in detail below with reference to the drawings.

FIGS. 3 and 4 show an embodiment of a full adder used in the adding circuit of the present invention. Figure 3 shows a type 1 full adder,
1st digit addition number Ai, 1st digit addend Bi, 1st
It has a function of inputting a carry signal Ci to the digit and outputting a sum St of the first digit and a carry signal C1+1 to the i+1 digit. Further, FIG. 4 shows a type 2 full adder, which inputs the addition number Ai, the augend Bi, and the carry signal Ci, and outputs the sum Si and the carry signal C1+1 to the i+1st digit.
It has the function of outputting. In Figure 3,
1a and 2a are logic gates having a iiicMo S transistor structure, and both have the same function. Logic gate 1a (same as 2a) receives six input signals a - e, a=b=c=1 (high logic level)
or when a = d = e = 1, the output f,
-0 (low logic level), a = b = c = 0
or when a =, d = e = O, the output f =
1, and under input conditions other than the above, the output f becomes a high impedance state.

3a is a three-manpower (1, m, n) logic gate, where l = m = 1 or 1 = n = 1
When , the output becomes 10, when 1 = m = O or 1 = n = o, the output becomes -1, and when the input conditions are other than the above, the output becomes a high impedance state. 4a is a two-man power (q+, h) logic gate,
When g = 'h = 1, the output is =o7, g,
When =h=o, the output becomes =1, and under other input conditions, the output becomes a high impedance state. 5a, 6
a and Ryoa are inverters with a known 0MO8 configuration.

10a to 14a, 20a to 24a, 30a to 32a,
40a, 41a (d: P channel transistor, 15a to 19a, 25a to 29a.

33a to 35a, 42a, 43a are N channel.
Both transistors are shown with arrows attached to their source terminals. Logic gate) Connect the outputs of 1a and 2a in common, obtain the sum St at the connection point f, and create the logic gate 3a.
, 4a are commonly connected, and a carry signal Ci is sent to the connection point k.
Gain +1.

The outputs and sum St of logic gates 1a and 2a for input signals Af, Bi, and Ci are shown in Table 1 as a truth table,
In addition, the outputs of logic 3a and 4a and the carry signal Ci+
1 is shown in the truth table in Table 2.

Table 1 Table 2 As an example, if Ai=O, Bi=1, and Ci=o, then P-channel transistor 10a.

11a and 14a are turned on at the same time, the output of the logic gel 1a is 1, the logic gate 2a becomes a high output impedance, the sum Si becomes 1, and the P-channel transistor 3
0a and 32a are turned on simultaneously, the output of the logic gate 3a becomes 1, the logic gate 4a becomes a high output impedance, and the carry signal C1+1 becomes 1.

From the truth tables of Tables 1 and 2, S i+ CH+ 1
is expressed by the following equation, and it can be seen that it operates as a type 1 full adder.

5i=Ai■Bi■Ci C,=AiBi +B1C1+C1Ai1+1 Next, the addition time of the type 1 full adder shown in FIG. 3 is estimated.

If the input signals At, Bi, and Ci are input at the same time, the in/verters 5a, 6a, and 7a output the ring gate
Since it is input to a to 4a, the sum Si is the delay time of two stages of gates, one stage of inverter and one stage of logic gate (1a or 2a), and the carry signal C1+1 is similarly the delay time of one stage of inverter and one stage of logic gate (1a or 2a). This can be obtained within the delay time of one stage of gates (3a or 4a) and two stages of gates.

Next, the input signals At and Bi are input first, and later Ci
is input, when Ci arrives, the transistors to which At, Bi, At, and Bi of logic gates 1a to 4a are input are already in the appropriate state, whether it is on or off, so the sum is St is obtained by the delay time of the two gate stages of the inverter 5a and the logic gate 2a, and for the carry signal Ci+1,
Logical logic) can be obtained within the delay time of one stage of gates 3a.

Next, the type 2 full adder shown in FIG. 4 will be explained.

In Figure 4, 1b, 2b, 3b, 4b are 0MO8)
These are logic gates having a transistor configuration, and have exactly the same functions as 1a, 2a, 3a, and 4a in FIG. 3, respectively. sb, eb, and 7b are inverters having a known 0MO8 configuration.

1ob~14b, 20b~24b, 3ob~32b, 4
0b, 41b are P-channel transistors, 1
5b-19b, 25b-29b.

33b to ssb, 42b, j3b are N channel.
Both transistors are shown with arrows pointing to their sources. Logic gate) 1b, 2h outputs are commonly connected, sum St is obtained at the connection point, logic gate 3b,
Connect the outputs of 4b in common and send a carry signal C1+1 to the connection point.
get.

Logic gate 1b for input signals Ai, Bi, Ci
, 2b and the sum Si in the truth table of Table 3,
Outputs of ethics gates 3b and 4b and carry signal Ci+1
is shown in the truth table in Table 4.

As an example in Table 4, Ai = 1, Bi ==O, Ci
If ==O(7) then N-channel transistor 1
5b.

16b and 17b turn on at the same time, the output of logic gate 1b becomes 0, and logic gate 2b becomes a high output impedance, resulting in a sum of SiO, and P-channel transistor 31b.
and 32b are turned on at the same time, and the output of 3b is 1.
, the logic gate 4bI'i has a high output impedance, and the carry signal C1+1 becomes 1.

From the truth tables of Tables 3 and 4, it can be seen that Sir 01+ 1 is expressed by the following equation and operates as a type 2 full adder.

5t=Ai OBi■ (Ci) C, +1=Ai13i + (Ci) (At■Bi) Next, the addition time of the type 2 full adder in Fig. 4 is estimated, but the input of the type 2 full adder in the figure Sum S from At, f3i, Ci
Since the number of gate stages up to i and carry signal C1+1 is exactly the same as the number of gate stages of the type 1 full adder shown in FIG. 3, the addition time is also the same.

FIG. 5 shows an embodiment of a 4-bit adder circuit according to the present invention. 51.63 in FIG. 6 is the type 1 full counter of FIG. 3, 52.54 is the type 2 full counter of FIG. 4,
The structure is such that a type 1 full adder is placed at the odd bit and a type 2 full adder is placed at the even bit. Component 1 in type 1 full adder 61 and type 2 full adder 62
8 to 7a and 1b to 7b are the same as the components with the same numbers in FIGS. 3 and 4, respectively.

Addition number (A4A3A2A1), addend number (B4B3B
2B1), carry signal C1 is input, and the sum of 4 bits (
S4S3S281 ) and carry signal C5 from the 4th digit
Output. Since the operation of each block 51 to 54 is clear from the explanation of FIGS. 3 and 4, detailed explanation will be omitted. Now, the addition number Ai, the addendum addition number i (i = 1 to 4),
If the carry signal C1 is input at the same time, the sum St is logical (1a).

Or 2a) 02 is the delay time of two stages of gates, one stage of logic gate (3a or 4a) and one stage of inverter, and is a critical path. Since the carry signal C5 has a delay time of three stages of gates from C2 to 06, it can be obtained with only a delay time of five stages of gates.

Generally, in the case of addition of n bits, the carry signal Cn+1, which is a gridical path, can be obtained with only a delay time corresponding to n+1 stages of gates. This is a value that is reduced to one-half of the critical path delay time of the conventional circuit shown in FIG. 2, which corresponds to 2 n + 2 stages of gates. In other words, it is possible to perform 7JO calculations at twice the addition speed as compared to the conventional circuit.

The carry signal Ci +1 + Ci +1 is a logic gate (
3a and +a, 3b and 4b), so
For example, it is easily possible to propagate a carry signal with a delay time smaller than the propagation delay of a signal propagation path on a board having a configuration in which transfer gates are connected in series.

As described in detail, according to the present invention, with a simple circuit configuration,
A full adder with twice the addition speed of the conventional one was obtained, and the carry signal propagation path, which is the critical path, was significantly shortened.
An adder circuit capable of high-speed addition operation is obtained, and its effects are extremely large.

[Brief explanation of the drawing]

FIG. 1 shows a conventional example of a full adder, FIG. 2 shows a conventional example of a 4-bit adder circuit, and FIGS. 3 and 4 respectively show type 1. FIG. 5 is a diagram showing an embodiment of a type 2 full adder, and FIG. 5 is a diagram showing an embodiment of a 4-bit adder circuit of the present invention. 1a-4a, 1b-4b...Logic gate, 6a
~7a, 6b~7b...Inverter.

Claims (2)

[Claims] (1) First. Second. Third. 4th. a sixth input, and the first +J2 + third inputs are both at high level; 4th. In at least one of the second cases in which both the sixth inputs are at high level, the output becomes low level, and the output becomes low level in the first case. In the third case where both the second and third inputs are at low level, or in the first case described above. 4th. In at least one of the fourth cases in which the fifth inputs are both low level, the output becomes high level, and when the input conditions are other than the first to fourth cases, the output becomes a high impedance state.
a second logic gate; and a sixth. 7th. The sixth input has an eighth input. In the 6th case where both the 7th inputs are at the level of No. In at least one of the sixth cases in which the eighth inputs are both high level, the output becomes low level;
Above 6th. In at least one of the seventh case in which the seventh inputs are both at low level, or the eighth case in which both the sixth and eighth inputs are at low level, the output becomes the NO level, and the output becomes the NO level. The 9th logic gate has a third logic gate whose output is in a high impedance state when the input conditions are other than the case of 8, and the 91st@10 input. In the ninth case in which both the tenth inputs are at high level, the output becomes low level, and in the ninth case described above, the output becomes low level. In the 10th case where both the 10th inputs are low level, the output becomes high level, and in the 9th case described above, the output becomes high level. and a fourth logic gate whose output is in a high impedance state when the input condition is other than the tenth case, and the first input signal is connected to the second input of the first logic gate and the second logic gate. a second input of the gate, an inverted signal of the first input signal is input to a fifth input of the first logic gate and a fourth input of the second logic gate; 2 input signals are input to the fourth input of the first logic gate and the third input of the second logic gate, and the inverted signal of the second input signal is input to the fourth input of the first logic gate. 3rd input and above 2nd input
a third input of the logic gate and a fifth input of the second logic gate; a third input signal is input to the sixth input of the third logic gate; The outputs of the second logic gates are commonly connected, and the third. The outputs of the fourth logic gate are connected in common to pass the first input signal to the seventh input of the third logic gate and the ninth input of the g4 logic gate.
the second input signal to the tenth input of the third logic gate; and the third human input signal to the tenth input of the third logic gate.
The inverted signal of the third input signal is inputted to the first input of the logic gate, or the inverted signal of the first input signal is inputted to the first input of the second logic gate. An inverted signal of the second input signal is applied to the eighth input of the third logic gate and the ninth input of the fourth logic gate. The third input signal is connected to the first input of the second logic gate, and the inverted signal of the third input signal is connected to the first input of the first logic gate. In the input of
An adder circuit characterized in that it is configured to receive inputs from each. (2) The adding circuit according to claim 1, wherein the third human input signal is an H-te increase input signal.