JPH04117815A - Programmable logic circuit - Google Patents

Abstract

PURPOSE:To realize a logic causing a sparce logic value table with a very small hardware, by providing a signal input means which selects one of plural input signals for a unit cell of each stage, inputs a noninverting signal (inverting signal) to a source of a 1st PMOS transistor(TR) and inputs an inverting signal (noninverting signal) to a source of a 1st NMOS TR to the logic circuit using a common drain of a 2nd PMOS TR and a 2nd NMOS TR of a unit cell of a final stage as an output. CONSTITUTION:N-sets of unit cells equal to number of input signals are arranged to the circuit and each of the unit cells such as a unit cell CLn+1 consists of a PMOS TRs (hereinafter QP) 1, 3 and NMOS TRs (hereinafter QN) 2, 4. An output yn-1 of a pre-stage unit cell CLm is fed to a common gate of the QP1, QN2 and an inverting signal Xn' and a noninverting signal Xn of an input signal are fed respectively to a source of the QP1, QN2 via a programmable switch. Optional combinations of EXOR and EXNOR up to N-sets of inputs are realized as the entire output by the programmable switch.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable logic circuit that realizes combinatorial logic of input signals in a programmable manner.

[Conventional technology]

Generally, arbitrary combinatorial logic is expressed by a truth table based on sum-of-products logic. In the truth table, for example, the input variable that appears in normal rotation for each product term of the input signal is ``
A matrix table is used in which input variables that appear in inversion are 0'' and input variables that do not appear are PAR''' are entered one row at a time on the horizontal axis.

Taking as an example the combinatorial logic y=)(, x2 +x2 X3 - Be1), the truth table is XI
It is given by X2 X3.

Based on this, conventional programmable logic circuits are
Any combinational circuit can be integrated by arranging D circuits and OR circuits in an array, applying the input signal and its inverted signal to the input of the AND circuit via a programmable switch, and applying the output of the AND circuit to the input of the OR5 circuit. The principle is to realize it in a Japanese style.

FIG. 3 is a circuit block diagram showing an example of a conventional programmable logic circuit.

When actually implemented using an MO3 circuit, it is often implemented by arranging a NOR circuit array and a NOR circuit array as shown in FIG. 3, but the principle remains the same. The analogy is (1
) formula, by passing the inverted signal of y through a two-stage NOR array,
−x2 +x2− X3 −・(3
) is correctly realized.

Such programmable logic circuits are widely used because if the logic expression is given by a compact truth table, the logic circuit can be easily realized by determining the ON-FF of the programmable switch in one-to-one correspondence with the table. ing.

[Problem to be solved by the invention]

However, this conventional programmable logic circuit
Regarding logic with sparse truth value representation, there was a problem that the hardware became large.

For example, EXOR with 3 inputs is 3/=X+■x2■X3 (■ represents EXOR)
+ X I X2 X3 + X I X2
X3'' (4) As the table becomes larger, the realized programmable logic circuit has to become larger.

[Means to solve the problem]

The programmable logic circuit of the present invention includes a first PMOS transistor having a common train and a gate, a first NMOS l-transistor, a first NMOS transistor having a common drain and a common gate, and a source connected to a power supply and a ground potential. It consists of a second P-Most transistor and a second N-MOS transistor connected to each other, the first PMOS transistor, the first NMOS transistor
connecting the common train of transistors to the second PMOS
The transistor is connected to the common gate of the second NMOS transistor, these two sets of PMO 8° NMOS transistors are used as unit cells, and a plurality of these unit cells are arranged in an array to form the second unit cell of the previous stage unit cell. PMO3)
Lunge meta. the first PMOS transistor of the common next stage unit cell of the second NMO3 transistor;
The NMO3 transistors are sequentially connected to the common gate I, and one of the plurality of input signals is selected for the unit cell of each stage, and a normal signal (inverted signal) is transmitted to the first PMOS transistor. and a signal input means for inputting an inverted signal (normal signal) to the source of the first NMO3 transistor, the second PMOS transistor of the unit cell in the final stage, the second NM
The common output of the O3 transistor is used as the common output, and the signal input means is characterized in that the normal rotation signal (inversion signal) is inputted via a block diagrammable switch.

Ru.

〔Example〕

Next, the present invention will be explained with reference to FIGS. 1 and 2.

FIG. 1 is a circuit block diagram showing an embodiment of the programmable logic circuit of the present invention.

In FIG. 1, N unit cells are lined up equal to the number of input signals, and each unit cell, for example, a unit cell CL11+,
is a PMOS transistor (hereinafter Qp>1.3 and NMOS
It consists of 2.4 transistors (hereinafter referred to as QN). Qp 1
, QN2, the output Vn-1 of the unit cell C1 in the previous stage is added to the common gate of QN2, and Qpl.

The sources of QN2 each have an inverted signal Xn of the input signal,
A normal rotation signal Xn is applied via a programmable switch (as shown). Qp3 and QN4 have an inverter configuration, and a signal from the common drain of Qp 1 and QN 2 is applied to the next stage unit cell CL, +2 via this inverter.

When the output signal 3'I+-1 of the unit cell Cl-6 in the previous stage is input to the unit cell CL, . . . , and the inverted signal xn and the normal rotation signal For the output 3'n of n, , the following is obtained: y,=sentence-■yn-1 =xn ■Y n-1...(6).

Therefore, the total output can be any EXOR of up to N total inputs by programmable switches.

It can be seen that the combination of EXNOR can be realized.

FIG. 2 is a circuit diagram of a 3-input EX○R circuit showing a series of application examples of the present invention, which is realized as an extremely simple circuit with a small amount of hardware in which four unit cells are connected in an array.

〔Effect of the invention〕

As explained above, the present invention is based on EXOR (EXNOR)
By arranging circuits in an array and applying input signals using signal input means (programmable switches), it is possible to realize the logic of a sparse truth table with very small hardware.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of the programmable logic circuit of the present invention, FIG. 2 is a circuit diagram of a three-input EXOR circuit showing a series of application examples of the present invention, and FIG. 3 is a circuit diagram of a conventional programmable logic circuit. FIG. 2 is a circuit block diagram showing an example. ], , 2-PMO3 transistor (Qp), 34 ・
NMOS transistor (QN), Cl-1CI-n+1
, CL n+2・unit cell.

Claims (1)

[Claims] 1. A first PMOS transistor and a first NMOS transistor each having a common drain and a common gate, and a second NMOS transistor having a common drain and a common gate, respectively, and whose respective sources are connected to a power supply and a ground potential. P-
It consists of a MOS transistor and a second N-MOS transistor, the first PMOS transistor, the first
The common drain of the NMOS transistor of
is connected to the common gate of the PMOS transistor and the second NMOS transistor, and these two sets of PMOS, N
A MOS transistor is used as a unit cell, and a plurality of these unit cells are arranged in an array to form the second P of the previous unit cell.
The common drain of the MOS transistor and the second NMOS transistor is connected to the first PMOS of the next stage unit cell.
The transistors are sequentially connected to the common gate of the first NMOS transistor, and one of the plurality of input signals is selected for the unit cell of each stage to send a normal signal (inverted signal) to the first NMOS transistor. Input the inverted signal (normal signal) to the source of the PMOS transistor and the first N
A programmable logic circuit comprising signal input means for inputting a signal to a source of a MOS transistor, and outputting the common drain of the second PMOS transistor and the second NMOS transistor of the unit cell in the final stage. 2. The programmable logic circuit according to claim 1, wherein the signal input means inputs the normal rotation signal (inverted signal) via a programmable switch.