JPS6264124A - Programmable logic device - Google Patents

Abstract

PURPOSE:To prevent waste of input/output terminals, deficiency of input terminals and to utilize effectively the terminals by providing plural input line pairs to at least one input terminal or an input/output terminal. CONSTITUTION:An input signal is fed through a couple of inputliens 32-1, 32-2 driven by a drive circuit 34-1 with respect to the input terminal 30-1, and the input signal synchronized by a register 8 is fed through a couple of the input lines 32-3, 32-4 driven by a drive circuit 34-2. This is applied similarly relating to other input terminal 30-l. A tri-state buffer circuit 26 is controlled by an output enable signal OE and when the circuit 26 is turned on, the input/output terminal 3 acts like an output terminal and when turned off, the terminal 36 acts like an input terminal. When the terminal 36 acts like an input terminal, a couple of input lines 40-1, 40-2 go to input lines for the input terminal and other couple of input lines 40-3, 40-4 are input lines for feedback.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a programmable logic device (P) that includes a programmable array and can configure any logic circuit by programming the array.
LD).

Programmable logic devices include PLA (PLA) in which both the AND and OR arrays are programmable.
programmable logic array), PAL with programmable AND array and fixed OR array
(programmable array logic), and those in which the AND array is fixed and the OR array is programmable.

(Prior art) In a programmable logic device, for l input signals (including feedback input input signals),
A pair of input lines is provided for supplying the AND array with an inverted signal of its input signal and an input line supplying a non-inverted signal.

In conventional programmable logic devices, there is generally one pair of input lines corresponding to one input terminal and one input/output terminal (see, for example, US Pat. No. 4,124,899).

Recently, as shown in FIG. It is possible to select whether to supply the output signal of the register (flip-flop) 8 which inputs the signal from
OR.

Either directly supply the output signal from the sense circuit 14-1, or
A programmable logic device that can select whether to supply the output signal of the register 16 that inputs the output signal from the OR sense circuit 14-1 or directly supply the input signal from the input/output terminal 12. (in this case PLA) is known. However, even in this programmable logic device, there is only one pair of input lines corresponding to one input terminal or input/output terminal.

In addition, in Fig. 5, 18-1.18-2°...
... is a human force line drive circuit, 20-1 to 20-n are product term lines,
22-1 to 22-r+ are AND sense circuits, 24-1.
. . . is an output line, and 26 is a three-state buffer circuit. Input line 2-1.2-2. . . . and the intersections of the product term lines 20-1 to 20-n and the output line 24-1
.

However, in a programmable logic device as shown in FIG. 5, the register 16 on the input/output terminal side
If used as a state storage register for feedback to the AND array, the input/output terminal 12 would be wasted. In other words, the input/output terminal 12 only becomes capable of taking out unnecessary outputs from the status register 16;
It cannot be used as an input terminal.

Furthermore, on the input terminal side, if it is attempted to use both a synchronized input using the register 8 and an asynchronous input, two input terminals are required.

Although programmable logic devices generally have a limited number of inputs and outputs due to the limited number of package pins, conventional methods have not been able to make effective use of the limited input pins and input/output pins. hard.

(Objective) An object of the present invention is to provide a programmable logic device having a circuit configuration that can effectively utilize input terminals and input/output terminals.

(Configuration) In the programmable logic device of the present invention, at least one of the input terminal and the input/output terminal has an input line that supplies an inverted signal of one signal to the AND array and a non-inverted signal. Two or more pairs of input lines are arranged.8 Hereinafter, embodiments will be specifically described.

FIG. 1 shows an embodiment in which the present invention is applied to a PLA in which both an AND array and an OR array can be programmed. Note that the same symbols are used for the same parts as in the circuit of FIG. 5.

The input terminal 30-1 is connected to the IWjA dynamic circuit 34-1 that drives the input lines 32-1 and 32-2, and to the input of the register 8. The output of register 8 is connected to input line 32-3.3.
A 1 drive circuit 34-2 that drives 2-4 is connected. Of the pair of input lines 32-1 and 32-2 connected to the yJA dynamic circuit 34-1, the input line 32-1 supplies a non-inverted signal of the input signal from the input terminal 30-1 to the AND array. , input line 32-2 supplies an inverted signal of the input signal from input terminal 30-1 to the AND array. Also, a pair of input lines 32-3. connected to the drive circuit 34-2.
32-4, the input line 32-3 supplies a non-inverted signal of the output signal of the register 8 to the ΔND array;
4 supplies an inverted signal of the output signal of register 8 to the AND array. in this way.

For input terminal 30-1, input lines 32-1 and 32-
2 and a pair of input lines 32-3 and 32-4.

All input terminals 3O-fl (in the same way).

Two pairs of input lines are provided.

For the input/output terminal 36, two input line drive circuits 38-
1.38-2 is located. A switch SW2 is connected to the input side of the drive circuit 38-1, and the drive circuit 38-2
A switch SW1 is connected to the input side of the switch SW1. A pair of inputs a40-1 and 40- are provided on the output side of the drive circuit 38-1.
2 is connected and input! ! A40-1 is switch S
A non-inverted signal of the signal selected by W2 is supplied to the AND array, and an input line 40-2 supplies an inverted signal of the signal selected by switch SW2 to the AND array. Further, a pair of input lines 40-3 are also connected to the output side of the drive circuit 38-2.
and 40-4 are connected, and the input fi40-3 ANDs the non-inverted signal of the signal selected by the switch SWI.
Input line 40-4 supplies an inverted signal of the signal selected by switch SWI to the AND array.

OR sense circuit 14-1 connected to output and force line -24-1
The output side of is connected to the C terminal of the switch SWI, the input terminal of the register 16, and the b terminal of the switch SW3.

The Q output terminal of the register 16 is connected to the C terminal of the switch SW3, and the ζ output terminal of the register 16 is connected to the switch SWI.
is connected to the B terminal of the switch SW2 and the C terminal of the switch SW2.

The switch SW3 is connected to a three-state buffer circuit 26, and the three-state buffer circuit 26 is connected to an input/output terminal 36. Further, the input/output terminal 36 is connected to the C terminal of the switch SWI, the C terminal of the switch SW2, and the input terminal of a register 42, and the Q output terminal of the register 42 is connected to the b terminal of the switch SW2.

Input line 32-1.32-2. ......, 40-1゜40-2, ------ and product term a 20-1 to 20-
Each intersection with n and the product term with output [24-1,...
3, an element is provided which can be programmed into a conducting state or a non-conducting state.

Next, the operation of this embodiment will be explained.

Regarding the input terminal 30-1, an input signal is supplied by a pair of input lines 32-1 and 32-2 driven by a drive circuit 34-1, and a pair of input lines 32-2 driven by a drive circuit 34-2. 3 and 32-4 provide synchronized input signals in register 8. Other input terminal 30-
The same applies to individuals.

Regarding the input lines 40-1 to 40-4, the switch SWI
The output signal of OR sense circuit 14-1, register 1
6, the output signal or the input signal from the input/output terminal 36 is selected and supplied to the input lines 40-3 and 40-4, and is input/output by the switch SW2.

The input signal from the output terminal 36, the Q output signal of the register 42, or the I output signal of the register 16 is selected and the input signal is sent to the input line 40.
-1.40-2.

The three-state buffer circuit 26 is controlled by the output enable signal OE, and the three-state buffer circuit 26
When is on, the input/output terminal 36 acts as an output terminal,
When the three-state buffer circuit 26 is off, the input/output terminal 36 acts as an input terminal. Switch SW3 is O
Output signal of R sense circuit 14-1 or Q of register 16
This is a switch for selecting an output signal and outputting it to the input/output terminal 36 via the three-state buffer circuit 26.

Now, for example, register 16 is used as a status register for feedback to the AND array, and switch SW
1 is connected to the b terminal, the input/output terminal 36 can be used independently as an input terminal by connecting the switch SW2 to the C terminal or the b@ terminal. In that case, the pair of input lines 40-1 and 40-2 serve as input lines for input terminals, and the other pair of input lines 40-3 and 40-4 serve as input lines for feedback. - In the embodiment shown in Fig. 1, switches SWI to SW3 are A
It can be configured using storage elements that configure an ND array or an OR array, and a transfer gate, an AND gate, an OR gate, or the like. Figure 2 shows an example of configuring a switch using FAMOS, which is an EPROM, as a memory element.
It is shown in Figure 4.

Figure 2 shows two FAMO5QI 1. This shows a circuit that outputs a high-level signal to one of four output signals (selection signals) Sa''Sd using Ql2.

FAMoS memory transistor QI 1. In a circuit including an NMo5 transistor Q12 and a PMOS transistor Q13, M connected to the power supply terminal (Vcc)
OS transistor Q13 is a pull-up load resistance element,
MOS transistor Q12 is a memory transistor Qll
This is a voltage limiting transistor to suppress the drain voltage of the transistor. A control gate of memory transistor QLI is connected to a power supply terminal (Vcc).

Node N1 between MOS transistors Q12 and Ql3 is connected to one input of AND circuits 60 and 62 via an inverter circuit 50, and
Connected to one input of circuit 64,66.

The circuit including the memory transistor Q21, the NMOS transistor Q2-2, and the r'MOS transistor Q23 is configured in exactly the same way as the circuit including the memory transistor Qll, the NMOS transistor Q12, and the PMO5+- transistor Q13. and Q23 are connected via an inverter circuit 54 to the other input of an AND circuit 60.64, and via inverter circuits 54 and 56 to the other input of an AND circuit 62.66.

Memory transistor Ql! , Q21 is provided separately, but is not shown.

When FAMOS is programmed, the threshold value becomes higher than Vcc and enters the cut-off state, so the memory transistor Ql 1. If Q21 is programmed, Nl, N
2 is a high level. In this way, depending on whether the memory transistors Qll and Q21 are programmed or not, the output signal (selection signal) Sa-=Sd is as shown in the table below.
Either one will be at a high level.

In the table, P represents the programmed state of the memory transistor and E represents the unprogrammed state of the memory transistor.
By setting a − S d as the gate signals of the three transfer gates 70, 72, and 74 shown in FIG.
A switch that switches between three terminals a, b, and C can be configured.

Further, these selection signals 5a=Sd are applied to three (7) AND circuits 80, 82, 84 . . . shown in FIG. ! = AND circuit 80.82 of the switch circuit consisting of the OR circuit 86.
By using 84 control inputs, 3 terminals a, b, c
It is possible to configure a switch to change the The same applies to a switch that switches between two terminals.

Although the embodiment shown in FIG. 1 relates to a PLA in which both the AND array and the OR array are programmable, the present invention is also applicable to a programmable logic device in which either the AND array or the OR array is programmable. Of course it can be done.

(Effects) In the present invention, a plurality of input line pairs are provided for at least one input/output terminal or output terminal, so even in the case of feedback input or input via a register, etc.
There is no need to waste input/output terminals or to run out of input terminals. Therefore, it becomes possible to effectively utilize the terminals in a programmable logic device despite the general limitation on the number of terminals in a package.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a circuit that generates a selection signal constituting a switch in the same embodiment, and FIGS. 3 and 4 are in accordance with the same embodiment. Oke-
Circuit diagram 5 shows a three-terminal switch.
It is a circuit diagram showing an example of A. 20-1 to 20-n; product term line; 30-1 to 30-Q; input terminal; 32-1 to 32-4. ...40-1 to 40-4
．． ...; Input line, 36; Input/output terminal.

Claims (3)

[Claims] (1) For at least one of the input terminals and input/output terminals, there are two or more pairs of input lines that supply an inverted signal of one signal to the AND array and input lines that supply a non-inverted signal. A programmable
logic device. (2) A terminal in which two or more pairs of input lines are arranged is an input/output terminal, and a pair of input lines is arranged in an OR array between the pair of input lines and the OR array and the input/output terminal. The programmable logic circuit according to claim 1, further comprising a switch circuit that connects to one of the wirings connected to the input/output terminal and connects another pair of input lines to one of the wirings connected to the input/output terminal.
device. (3) A terminal where two or more pairs of input lines are arranged is an input terminal, and the signal from that input terminal is directly supplied to one input line pair, and the signal is directly supplied to the other input line pair. 2. The programmable logic device according to claim 1, wherein the programmable logic device is connected so as to be supplied with an output signal of a register that receives a signal from an input terminal.