JP2643716B2 - Bus driver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus driver.
More specifically, the present invention relates to a bus driver (output buffer) of each circuit block in a circuit system in which a plurality of circuit blocks are connected to a common bus among semiconductor integrated circuits.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional example in which a plurality of circuit blocks are connected to a common bus and mutually transfer data. FIG.
In, for example, data output from the CPU 126 is sent to the memory 125 through the common bus 101. In the next cycle, data is sent from the memory 125 to the common bus 101, and the data is taken into the hard disk 127.

Next, a conventional example in which data is transferred between two circuit blocks having input / output ports will be described with reference to FIG. In the circuit system shown in FIG. 2, for example, data is transferred from the first circuit block 117 to the second circuit block 118 in the first step, and is transferred from the second circuit block 118 to the first circuit block 117 in the second step. Transfer data. In this case, in the first step, the output buffer 121 in the first circuit block 117 is in the output enable state, and the output buffer 123 in the second circuit block 118 is in the output disable state. In this state, data is sent to the common bus 101 via the output buffer 121 in the first circuit block 117,
In the circuit block 118 of FIG.

Next, in a second step, the output buffer 121 in the first circuit block 117 is in the output disable state, and the output buffer 123 in the second circuit block 118 is in the output enable state. In this state, data is sent to the common bus 101 through the output buffer 123 in the second circuit block 118, and is taken in through the input buffer 122 in the first circuit block 117.

[0005]

Since the conventional circuit system is as described above, the moment the data transfer destination is switched,
From the first circuit block 117 to the second circuit block 11
Depending on the timing of the signal for controlling the output enable / disable of the output buffers 121 and 123 at the moment of switching to 8, there is a possibility that a state where both output buffers are enabled, a so-called bus conflict state, may exist for a certain period.

For this reason, when the output signal from the first circuit block 117 is at the “high” level and the second circuit block 1
When the output signal from the output buffer 18 is at the “low” level, the power supply-ground is connected between the output buffer 121 of the first circuit block 117 and the output buffer 123 of the second circuit block 118 via the common bus 101. A through current will flow between them.

Particularly, since the output buffers 121 and 123 are connected to the common bus 101 having a large load, a buffer having a large driving capability (transistor size) is required to execute data transfer at a high speed. CM
In a circuit system composed of MOS transistors represented by an OS, if a transistor having a large drive capacity is used for an output buffer, the above-mentioned through current becomes excessive, the power supply voltage decreases, and the circuit malfunctions. There has been a problem that latch-up occurs due to an excessive through-current triggered and the entire circuit system is destroyed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a bus driver capable of suppressing a through current generated at a moment when a plurality of output buffers are simultaneously enabled.

[0009]

According to a first aspect of the present invention, there is provided a bus driver for driving a common bus to which a plurality of circuit systems are connected. An output buffer including a high drive element and a low drive element for driving the common bus in a low state; a level detection means for detecting a signal level of the common bus; and the common buffer according to a detection result of the level detection means. When the signal level of the bus becomes equal to or higher than a certain value, the driving capability of the high drive element is suppressed, and when the signal level of the common bus becomes equal to or lower than a certain value, the low drive element is turned off. And a drive control circuit for suppressing the drive capability.

[0010]

According to the present invention, when the signal level of the common bus becomes high in an instantaneous bus conflict state,
The driving ability of the high driving element provided in the output buffer connected to the common bus is suppressed, and when the signal level of the common bus becomes low, the driving ability of the low driving element provided in the output buffer connected to the common bus is suppressed. Therefore, it is possible to suppress a through current flowing through the common bus.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A bus driver according to one embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a circuit system including a bus driver according to an embodiment of the present invention. CMOS type circuit systems 17 and 18 including the bus driver of the present embodiment are connected to the common bus 1.
Although the details of the circuit system 18 are not shown, it has the same configuration as the circuit system 17.

A bus driver provided in the circuit system 17 shown in FIG. 1 includes an output buffer 21 for driving the common bus 1 in a high or low state, a level detecting means 22 for detecting a signal level of the common bus 1, When the signal level of the common bus 1 becomes high in response to the detection result of the level detecting means 22, the driving capability of the output buffer 21 in the high state is suppressed, and when the signal level of the common bus 1 becomes low, the output buffer 21 becomes the low state. And an inverter 13 as an input buffer.

The output buffer 21 includes transistors (FETs) 2 and 3 as P-channel high drive elements and N
Transistor (FE as channel low drive element)
T) 4, 5 are used, and in particular, transistors 2 and 4 each having a larger driving capability than transistors 3 and 5 are used.

The level detecting means 22 includes a Schmitt inverter 12 connected to the common bus 1 and a first inverter 11 connected to the Schmitt inverter 12 in series. Assuming that the power supply voltage is 5 V, the Schmitt inverter 12 has a hysteresis of 3 V around 2.5 V.
The one with the characteristic of the degree is used.

The output signal line 14 is a signal line for sending a signal from the circuit system 17 to the common bus 1.
Reference numeral 15 denotes an output enable terminal, which is "low" active.

The drive control circuit 23 includes a pair of NANDs (NA
ND) gates 7 and 8 and a pair of NOR (NOR) gates 9 and 10, and an enable signal is sent from the output enable terminal 15 to the pair of NAND gates 7 and 8 via the second inverter 6. An enable signal is directly sent from the output enable terminal 15 to the pair of NOR gates 9 and 10.

The detection signal from the Schmitt inverter 12 is sent to the NAND gate 8 and the NOR gate 9. The output signal of the first inverter 11 for inverting the detection signal of the Schmitt inverter 12 is supplied to the NAND gate 7.
And to the NOR gate 10. Further, the signal from the output signal line 14 is sent to the NAND gates 7 and 8 and the NOR gates 9 and 10, respectively.

On the other hand, the output side of the NAND gate 7 is connected to the gate of the transistor 3 as a high drive element,
The output side of the NAND gate 8 is connected to the gate of the transistor 2 as a high drive element. The output side of the NOR gate 9 has a transistor 4 as a low drive element.
And the output side of the NOR gate 10 is connected to the gate of the transistor 5 as a low drive element. In FIG. 1, reference numeral 16 denotes a signal line in the circuit system 17.

Next, the circuit system 17 constructed as described above,
The operation of 18 will be described by taking as an example a case where a signal is transferred from the circuit system 17 to the circuit system 18. In the following, it is assumed that the circuit operation is positive logic.

In the initial state, the signal level of the common bus 1 is "low", and the circuit system 17 outputs a "high" level signal. In the initial state, the output enable terminal 15 is in a "high" state, and all the transistors are off.

When the common bus 1 is at "low" level, the detection signal of the Schmitt inverter 12 becomes "high",
At this time, the output signal of the first inverter 11 is "low".
Becomes In this state, when the output enable terminal 15 goes "low" and the output signal line 14 goes "high", the transistor 2 connected to the NAND gate 8 is turned on. 1 is raised from "low" to "high".

When the signal level of the common bus 1 becomes 4 V or more, the output of the Schmitt inverter 12 becomes "low", and the transistor 2 having a large driving ability is turned off. Turn on. That is, when the signal level of the common bus 1 becomes 4 V or more, the bus driver of this embodiment operates so as to switch from the transistor 2 having a large driving ability to the transistor 3 having a small driving ability.

The signal level of the common bus 1 is "high".
In the case of outputting a "low" level signal from the circuit system 17, similarly, first, the transistor 4 having a large driving capability is turned on to rapidly change the signal level of the common bus 1 from "high" to "high". Low. When the signal level of the common bus 1 becomes 1 V or less, the Schmitt inverter 1
2 becomes "high", the transistor 4 having a large driving capability is turned off, and the P-channel transistor 5 having a small driving capability is turned on instead. That is, the common bus 1
When the signal level becomes 1 V or less, the bus driver of this embodiment operates so as to switch from the transistor 4 having a large driving capability to the transistor 5 having a small driving capability.

Therefore, first, data transfer with the output signal level of "high" is performed from the circuit system 17 to the circuit system 18 as described above, and as the next step, data transfer from the circuit system 18 to the circuit system 17 is performed. When the output signal level becomes “low”, the bus driver (not shown) in the circuit system 18 has the same circuit configuration as the circuit system 17.
The signal level of the common bus 1 is rapidly reduced to "low" by an N-channel transistor having a large driving capability.

At the moment of this switching operation, if the output buffer 21 of the circuit system 17 is also enabled, the power supply (not shown) switches the P-channel transistor 3 of the circuit system 17 from the circuit system 18 via the common bus 1. A through current may flow to the ground through the output N-channel transistor.

However, since the P-channel transistor 3 of the circuit system 17 has a small driving capability, the through current becomes very small, and it is possible to prevent an overcurrent such as a latch-up from flowing.

Similarly, the circuit systems 17 to 1
8, the data transfer with the output signal level “low” is performed,
As the next step, when data is transferred from the circuit system 18 to the circuit system 17 and the output signal level becomes "high", the N-channel transistor 5 of the circuit system 17 is driven even if a through current flows. Since the capability is small, the through current becomes very small, and it is possible to prevent an overcurrent from flowing which may cause latch-up.

The present invention is not limited to the embodiment described above, and various modifications can be made within the scope of the invention. For example, in the above-described embodiment, the C-MOS type circuit system has been described. However, the n-MOS type or p-MOS type circuit system and the bipolar circuit system can be appropriately switched by changing the driving capability of the output buffer. The same operation and effect as those of the embodiment can be exhibited.

[0029]

As described above, according to the present invention, an output buffer including a high drive element for driving a common bus in a high state and a low drive element for driving a common bus in a low state, and a common bus Level detecting means for detecting the signal level of the common bus, and when the signal level of the common bus becomes "high" in accordance with the detection result of the level detecting means, the driving capability of the high drive element is suppressed, and the signal level of the common bus becomes low. By providing a drive control circuit that suppresses the drive capability of the low drive element when the signal goes low, the drive capability of the high drive element is suppressed when the signal level of the common bus is high. When the signal level of the common bus is “low”, the drive capability of the row drive element is suppressed. By suppressing the penetration power flowing to de side can provide a bus driver capable of stable operation exerted.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a circuit system including a bus driver according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional circuit system.

FIG. 3 is a block diagram of a conventional circuit system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Common bus 13 Inverter 17 Circuit system 18 Circuit system 21 Output buffer 22 Level detection means 23 Drive control circuit

Claims (1)

(57) [Claims] 1. A bus driver for driving a common bus, comprising: a high driving element for driving a common bus to a high state; and a low driving element for driving the common bus to a low state. Comprises a parallel circuit of a first MOS transistor having a large driving capability and a second MOS transistor having a small driving capability. The low drive element includes a third MOS transistor having a large driving capability and a fourth MOS transistor having a small driving capability. A level detecting means for detecting a signal level of the common bus; and a first signal for changing the signal level of the common bus from low to high in accordance with a detection result of the level detecting means. M
An OS transistor is turned on, and when the signal level of the common bus becomes equal to or higher than a predetermined level, the first MOS transistor is turned off.
When the OS transistor is turned on and the signal level of the common bus is changed from high to low, the third M
An OS transistor is turned on, and when the signal level of the common bus falls below a predetermined level, the third MOS transistor is turned off.
A bus driver comprising a drive control circuit for turning on an OS transistor.