JPH0137008B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamically driven CMOS logic array.

Storage devices (hereinafter referred to as memory) used in computers, etc. are realized by a regular arrangement (array) of cells with the same structure, and since they are mass-produced commercially, both input and output are standardized. in the direction. On the other hand, various control circuits are becoming more and more complex, with logic circuits such as computers; interface circuits, etc.
It has been diversified. Therefore, it is very difficult to design the control circuit in a unified manner, and various circuits are appropriately combined. As one of the solutions for the above direction, logic circuits are logically AND and OR
Focusing on the fact that it is composed only of combinations with AND
Logic arrays are beginning to be used, in which the and OR circuits are arranged in an array structure in advance, and the contacts of the array are connected or opened according to the required logic. It is also called a program logic array (PLA) because the user can freely configure the logic settings. This is similar to a read-only storage device (hereinafter referred to as ROM) in that it produces the necessary output according to the address signal, but ROM must determine the output word for every combination of address signals, but PLA Since it operates in response to address signals as if it had an internal address decoder, only the necessary outputs need be configured internally, resulting in an extremely simple structure. For purposes of use, ROM
While PLA is suitable for holding large amounts of the same type of data, PLA has a relatively small capacity and is custom-made, making it suitable for a variety of applications, especially control circuits.

For example, the logical function is AND− of f ₁ = ₁ x ₂ + x ₂ x ₃
Since it is a two-stage OR configuration, x ₂ , x ₂ x ₃
Use an AND array to realize the sum of the two using an OR array. PLA is therefore an array designed to have a structure in which the input is input to an AND array, the logical product created by this is input to an OR array, and the sum of these is output.

To realize this PLA with a MOS gate circuit,
As for the drive method, (a) Both arrays are static, (b) AND array is static/OR.
There are three possibilities: (c) both arrays should be dynamic. (c) Both arrays should be dynamic. The all-dynamic method (c) can minimize the area of the PLA in terms of power consumption, but as explained below, it has the drawbacks of slow speed and the need for a special clock for dynamic drive. Referring to Figure 1, the conventional dynamic method
Explain how PLA works. Figure 1 shows a 2-input, 4-output PLA, with 1 being an AND array and 2 being an OR array, and these arrays have grid points that connect to the input and output lines of each array. Typically, MOSFETs are used as lattice points, and the junctions of specific FETs are destroyed to separate them from the array in order to obtain the desired logic function.

Here, P in non-suffix parts such as P _0P and N _0S indicates a P-channel FET (P-type FET), and N indicates an N-channel FET (N-type FET). Also, from a practical standpoint, in the following, the AND array is the first gate circuit,
The OR array will be referred to as the second gate circuit.
P _0P to _{P 3P} are P-type FETs for precharging the first gate circuit 1, and N _0S to _{N 3S} are N-type for discharging.
FET, (N ₀₁ N ₀₃ ), (N ₁₀ N ₁₃ ), (N ₂₁ N ₂₂ ),
(N ₃₀ N ₃₂ ) realizes the AND for the input signals I ₀ , ₀ , I ₁ , ₁ . P _4P to _{P 7P} are P-type FETs for precharging the second gate circuit 2, N _4S to _{N 7S} are N-type FETs for discharging, and N _r0 to _{N r7}
constitutes the logical sum of the outputs of the first gate circuit 1.
The circuit operation of this dynamic system will be explained. First, when the clock pulse _A becomes low level, the precharge FETP _0P ~ P _3P turns on, and the discharge charge FETN _0S ~ N _3S turns off, so the output line (also called product term line) of the first gate circuit 1 R ₀ ~ _R3
is precharged. Next clock pulse _A
When becomes high level, FETN _0S for death charge ~
_N3S is on, pre-charge FETP _0P to _P3P are off and disconnected from the power supply V _CC . At this time, the output line
The levels of R ₀ to R ₃ are maintained at the "1" level precharged by the input signals I ₀ , ₀ , I ₁ , ₁ , or are discharged to the "0" level. Since the second gate circuit has exactly the same structure as the first gate circuit, its operation depends on the level of _B and the output lines R ₀ to R ₃ of the first gate circuit. When the clock pulse _B becomes a low level, the precharge FETP _4P to _P7P are turned on and the discharge FETN _4S to _N7S are off, so the output lines _O0 to _O3 are precharged. When _B becomes high level, the discharge FETN _4S to N _7S are turned on, the pre-charge FETP _4P to P _7P are turned off, and the output line is disconnected from the power supply V _C. The output lines O ₀ to _{O 3} are the output lines R ₀ to O 3 of the first gate circuit 1.
Precharged state “1” due to the state of R ₃
level or descharged state “0”
level. The operating characteristics of PLA are shown in the time waveform diagram in Figure 2. Here, V _A and V _B represent the voltage levels of the respective lines. The t ₀ period is a period in which both the first gate circuit and the second gate circuit are precharged. In period t ₁ , the level is _A high and the first
The gate circuit enters a discharge state, while φ _B remains at a low level, so the second gate circuit is in a precharge state. Only in period t ₂ does φ _B go high, and the level of the output line of the second gate circuit appears as a result of the level of the output line of the first gate circuit. The reason for providing these special clock pulse periods t ₀ , t ₁ , and t ₂ is explained in Japanese Patent Laid-Open No. 146549/1983.

In the above drive method, the conditions for the clock pulse are that the high level time of _A is greater than t _A + t _B and the high level time of _B is greater than t _B. Here
t _A and t _B are discharge times of the first and second gate circuits. Normally, the clock pulse is synthesized from the basic clock, so in the case of a three-phase clock, t ₀ = t ₁ =
t ₂ , and in the case of a four-phase clock, t ₀ =t ₁ and t ₂ =2t ₆ .
Therefore, the PLA access time is 2t ₀ or 3t ₀ (t ₁ +t _{2 )} , and even if the basic clock is made faster, no faster access time can be obtained. As described above, the conventional PLA configuration has the drawbacks of requiring two special clock pulses and not being able to provide a fast access time.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a high-speed logic array that is dynamically driven by a single clock pulse train.

The logic array according to the present invention includes a first gate circuit that uses transistors of one conductivity type to form an AND array and receives an input signal, and an OR array using transistors of the opposite conductivity type to receive the output of the first gate circuit. a second gate circuit, each transistor of the first gate circuit is connected in series with the output line, each transistor of the second gate circuit is connected in parallel with the output line, and further includes a clock pulse a control circuit that turns on each transistor of the first gate circuit regardless of the input signal during a first logic level period of the clock pulse; and a control circuit that conducts each transistor of the first gate circuit during the first logic level period of the clock pulse. and means for precharging an output line, and obtaining an output from the second gate circuit during a second logic level period of the clock pulse.

The present invention will be described in detail below with reference to the drawings.
FIG. 3 shows an embodiment of the present invention.

The first gate circuit 1 constitutes an AND array, the second gate circuit 2 constitutes an OR array, and the NAND gate circuit 3 constitutes an input control circuit. The first gate circuit 1 is connected to the conventional AND array shown in Fig. 1 on the input side.
They are exactly the same except for the NAND circuit 3.
NAND gate 23 forces its output to 1 when _A is low level. The second gate circuit is completely different from that shown in Fig. 2, and uses the same clock pulse _A as the first gate circuit, and _N0P to _N3P are N for discharge.
type FET, and does not have a pre-charge FET.

The operating characteristics of this logic array will be explained with reference to the time waveform diagram of FIG. First, (a) _A is at a low level during the period t ₀ , and is used for pre-charge.
FETP _0P ~P _3P is turned on and used for discharge
FETN _0S ~N _3S are turned off. Also, due to discharge, all the outputs of the NAND circuit 23 on the input side become "1", so the output line of the first gate circuit 1
All R ₀ to _{R 3} are precharged. Furthermore, the second gate circuit 2 is for discharge.
FETN _0P to N _3P are on, and P ₀ to _{P 7} forming the logical sum are all off because the output lines of the first gate circuit are all precharged.

Therefore, the output lines _O0 to _O3 connected to the discharge FETNs _1P to _N3P are at "0" level.
(b) In the next period t ₁ , the clock pulse _A becomes high level, and the inputs I ₀ , ₀ , I ₁ , ₁ of the first gate are directly input to the first gate. Also P type
Since FETP _0P to P _3P are turned off and N-type FETN _0S to _{N 3S} are turned on, the output lines R ₀ to _{R 3} maintain the precharge state or are discharged depending on the input. In other words, the level corresponds to logical product. On the other hand, the second
Since _A is at a low level in gate circuit 2, FETN _1P to N _3P for discharge is turned off and the output line
O ₀ to _{O 3} are disconnected from the ground, and depending on the state of the output lines R ₀ to _{R 3} of the first gate, the discharged state "0" is maintained by turning on or off the P-type FETP ₀ to P ₇ , or is precharged and becomes “1”
become the level. Note that during the period t ₀ , the first gate circuit 1
The reason for forcibly setting the input level to a high level is to prevent malfunctions due to capacitance division.

The access time of the PLA of the present invention is the time from when the first gate circuit discharges to when the second gate circuit precharges.
Since precharging of the second gate circuit 2 starts immediately when the threshold values of FETP ₀ to P ₇ are exceeded, this is the minimum clock time including t _C at which the value of the output line becomes stable. As shown in Figure 2, the conventional method requires a minimum access time of t _A + t _B , but since t _C < t _A + t _B , the access time is extremely short, and FETs with fast rise times are often used. t ₁
= 2t ₀ , the time t ₀ itself can be made extremely small, and the access time t ₁ becomes much smaller.

As explained above, since the dynamic drive is performed using only one clock pulse without using the conventional special two clock pulses, the circuit configuration is easy and suitable for application to various control circuits. In addition, access can be made in twice the access time of the basic clock, and the frequency of the basic clock can be increased, making it possible to use high-speed operations that have not been possible until now.

[Brief explanation of drawings]

Figure 1 is a conventional PLA circuit diagram, Figure 2 is a circuit diagram of a conventional PLA.
FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a time chart showing the circuit operation of FIG. 3. DESCRIPTION OF SYMBOLS 1...First gate circuit, 2...Second gate circuit, 3...Input control circuit, _R0 to _R3 ...Output line (product term line), _O0 to _O3 ...Output line, 23... …NAND
circuit.

Claims (1)

[Claims] 1. A first gate circuit that configures an AND array using transistors of one conductivity type and receives an input signal;
a second gate circuit that configures an OR array using opposite conductivity type transistors and receives the output of the first gate circuit, each transistor of the first gate circuit being connected in series with the output line, and Second
Each transistor in the gate circuit is a CMOS logic array connected in parallel to the output line,
a control circuit that conducts each transistor of the first gate circuit regardless of the input signal during a first logic level period of the clock pulse; and a control circuit that conducts each transistor of the first gate circuit during the first logic level period of the clock pulse. means for precharging each output line, and obtaining an output from the second gate circuit during a second logic level period of the clock pulse.