JPH0220924A - Logic array - Google Patents

Abstract

PURPOSE:To obtain the logic array of high speed brought to dynamic driving by one clock pulse train by pre-charging each input line to the power source potential in a pre-charge period and interrupting each transistor and supplying an input signal to the input line in a sampling period. CONSTITUTION:A first gate circuit 1 and a second gate circuit 2 constitute an AND array and an OR array, respectively, a NAND gate circuit 3 constitutes an input control circuit, and a NAND gate 23 sets forcibly its output to '1' when a clock pulse phi'A is in a low level. In a period t0, phi'A is in a low level, pre-charge FETs P0P-P3P become ON, and discharge FETs N0S-N3S become OFF. As for the second gate circuit 2, discharge FETs N0P-N3P become ON, and also, P0-P7 for constituting OR all become OFF since the output line of the first gate circuit is pre-charged. In such a way, the circuit constitution is facilitated due to dynamic driving of only one clock pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamically driven CMOS Ronoc array.

Storage devices t (hereinafter referred to as memory) used in computers, etc. are realized by a regular arrangement (array) of cells with the same structure, and since they are mass-produced commercially, input and output are also standardized. in the direction. On the other hand, various control circuits have become increasingly multiple and diversified, including logic circuits for computers, interface circuits, etc. Therefore, it is extremely difficult to design control circuits in a unified manner, and various circuits are combined as appropriate. There is. As one of the solutions to the above-mentioned direction, we focus on the fact that a logic circuit is logically composed only of combinations of ANL) and OR, and arrange AND and OR in advance in a play structure as required. Logic arrays are beginning to be used in which contacts 1 of the array are connected or opened depending on the logic.

It is also called a program logic array (PLA) because the user can freely configure logic settings.

This is the same in that the read-only memory device (hereinafter referred to as ROM) can output the necessary output according to the address signal, but
ROM must define output words for all combinations of address signals, but PLA operates as if it has an internal address decoder for address signals, so it is only necessary to configure the necessary outputs internally. , an extremely simple structure is required. In terms of applications, while ROM is suitable for holding a large amount of the same type of data, PLA has a relatively small capacity and is custom-made and is suitable for a wide variety of applications, especially control circuits.

For example, the logical function is in the form of a two-stage structure of AND -OR of fl = XI XI +x, N3, so Xtxl.
XI Xg is realized by AND play, and the sum of both is realized by OR play.

PLA is therefore a play designed to have a structure in which the inputs go into an AND array, the logical product created by this goes into an OR array, and the sum of these goes out.

To realize this PLA with the MO8f -) circuit, the drive method is (a) both arrays are static, (0) AND play is static, OR array is dynamic, and h) both arrays are both static. I think the winner is the dynamic method.

The full dynamic method of (c) is P in terms of consumption and mother power.
Although the LA area can be minimized, as will be explained below, the speed is slow and a special lock is required for dynamic drive.

The operation of a conventional dynamic PLA will be explained with reference to FIG. FIG. 1 shows a 2-manpower, 4-output PLA, with 1 being an AND array and 2 being an OR array, and these arrays have lattice points that connect to the input and output lines of the respective arrays. MO8FETs are usually used at the lattice points to obtain the desired logical function.

Destroys the junction of a specific FET and eliminates play.

Here P. ,,No, P of the part that is not a suffix of 4
indicates a P-channel FET (P-type FET), and N indicates an N-channel FET (N-type FIT). From a practical standpoint, the AND array will be used as the first gate circuit below.

The OR array will be referred to as the second) late circuit.

Po, ~P3F are P-type F'ET + N08~N3. which precharge the first gate circuit 1. is an N-type FET for discharge, (N01Noρl (N10N15
) l (N21N22) 1 (N, .N, 2) is the input signal engineer. ,■. , 11. It realizes logical product for I. P4. ~P7. are P-type FETs for precharging the second r-to circuit 2, N4a to N7a are N-type FETs for discharging, and N08 to N37 are the first r-)
A logical sum of the outputs of circuit 1 is constructed. The circuit operation of this dynamic method will be explained. First, when the clock 79 pulse φ becomes low level, the precharge FET Po, ~P3
．． turns on, discharge FET N,...~N
6. is turned off, so the output lines (also referred to as product term lines) Ro to R3 of the first r-to circuit 1 are precharged. Next, when the clock pulse φ becomes high level, the discharge FETs No. to N3a are turned on.

Precharge FET pop-p4. is disconnected from the off stain source vcc. This crest output line R6-R3
The level is input signal engineering. , To, t, , T, either maintains the precharged state '1' level or r (charges and becomes @0' level. The second gate circuit is exactly the same as the first f-) circuit. Because of its structure, its operation is determined by the level of φ8 and the output line Ro-R of the circuit (1f-).When the clock pulse φ8 goes to a low level, the precharge FETs P4° to P7F are turned on and are used to charge the rIss. Since FETs N4. to N7m are off, the outputs WAOo to 05 are precharged.φ
When 8 reaches a certain level, discharge FETN4. ~
N7m is not on, FgT P4p for f recharge
-P7p is turned off and the output line is the power supply ■. be separated from And output I mackerel 0°~0. is the precharged state ""1# level and the discharged state'
Becomes an O# level. The operating characteristics of the PLA are shown in terms of time waveform factors in FIG. Here, VA and V represent the voltage levels of the respective lines.

The t0 period is a period in which both the first gate circuit and the second gate circuit are precharged. During the t1 period, the voltage becomes high level and the first gate circuit enters the discharge state, but
On the other hand, since φ8 remains at a low level, the second f-) circuit is in a precharged state. Only during period t1 does the signal go to a high level, and the level of the output line of the first r-gate circuit results in the level of the output line of the second gate circuit.

This special lock/arm period to I tt
t.

The reason for providing this is explained in Japanese Unexamined Patent Publication No. 146549/1983.

In the above driving method, the condition for the clock pulse is that the high level time of φ is longer than tA+tll and the high level time of +jB is longer than tB. Here tA.

ta is the first. This is the discharge time of the second gate circuit. Normally, the clock pulse is synthesized from the basic clock, so in the case of a three-phase clock, t, ztl = t.

For 4-phase clock t@”tl * tz = 2
It will be t6. Therefore, the access time of the PLA is 2t or 3t0 (tl + ts), and even if the basic clock is made faster, no faster access time can be obtained. As described above, the conventional PLA configuration has the drawbacks of requiring a special clock pulse 'k 2 +lIA and not being able to obtain a fast access time.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a high-speed logic array that is dynamically driven by a single clock pulse train.

A logic array according to the present invention has a plurality of output lines, a plurality of input lines, a gate connected to a selected input line, and a drain path connected between the selected output line and a voltage potential. means for precharging each output line to a ground potential during a precharge period; and means for precharging each input line to the power supply potential during the precharge period to turn off each transistor; /fsy
and means for supplying an input signal to the input line at the input line.

The present invention will be described in detail below with reference to the drawings. FIG. 3 shows an embodiment of the present invention.

The first gate circuit 1 #1 constitutes an AND array, the #I2 gate circuit 2 constitutes an OR array, and the NAND f-) circuit 3
constitutes an input control circuit. First gate circuit IFi
The conventional AND array shown in Fig. 1 and the NAND1 path 3 on the input side.
They are exactly the same except for one point. NAND gate 23
forces its output to 1 when φ is low level.

The second gate circuit is completely different from that shown in FIG.
, is an N-type F'ET for discharge.

In particular, it does not have an FET for precharging.

The operating characteristics of this logic array will be explained with reference to the time waveform diagram of FIG. First, (a) during the period t, φ is at a low level, and the precharge FET Po,
~P31F turns on and discharge FET N
o, ~N5. is turned off. Also, due to φ4, N on the input side
The outputs of the AND circuit 23 are all I'', so the first e
-) All output lines R6-R5 of circuit 1 are precharged. Furthermore, regarding the second (2) I'-) circuit 2, the discharge FETs No., A-N, are on, and P forming a logical sum. -R7 is turned off because all the output lines of the first gate circuit are precharged.

Therefore, the discharge F'ICT N, . . . ~N5. The output line connected to 0°~0. It is at the 0” level.
(b) In the next t4 period, the clock/intermediate pulse φ becomes high level, and the input to the first gate! . ,■. +11+11 is input as is to the first gate. Also, P type FET P
o, ~P3P is off, N-type FET No., ~N3. is turned on, so the output lines R6-R3 maintain a recharged state or discharge depending on the input. In other words, the level corresponds to logical product. On the other hand, 2nd f-) circuit 2
Since φ is at a low level, the discharge FET
N,, ~N5P is turned off, and the output lines 0°~03 are disconnected from the ground, and I is turned on or off by turning on or off the 9P type FET Po~P7 depending on the state of the output line R6~R3 of the first gate.
)'y'' maintains the activated state "0" or is precharged and becomes @1# level.In addition, during the period to, the input level of the first gate circuit 1 is forcibly set to high level. The next step is to prevent malfunctions due to capacity division.

The access time of the PLA of the present invention is the time from when the first gate circuit 1 discharges to when the second gate circuit recharges. Since precharging of the second r-) circuit 2 is immediately started when the threshold value of ~P2 is exceeded, this is the minimum clock time including tct- for which the value of the output line is stabilized. In the conventional method, as shown in Fig. 2, a minimum of tA + tB is required as the 7 access time, but the access time is extremely short as tc < tA + tlI. Even if t = 2t, it is possible to apply an extremely small pressure to the to1 body, and the access time t1 becomes much shorter.

As explained above, since it is driven by a single clock pulse instead of using the conventional special two clock pulses, the circuit configuration is easy and it is suitable for various control circuit applications. . In addition, access can be made in twice the access time of the basic clock, and the frequency of the basic clock can be increased, making it possible to use the system for next-high-speed operation, which was previously unusable.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional PLA, Fig. 2 is a time chart showing the circuit operation of Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4 is a circuit diagram of Fig. 3. FIG. 3 is a time chart diagram showing circuit operation. 1...First date circuit, 2...Second date circuit, 3
...Input control circuit, Ro-R, ...Output line (product term line) 1.0. ~03...Output line, 23...NAND circuit. Agent: Susumu Uchihara, patent attorney M2

Claims (1)

[Claims] a plurality of output lines, a plurality of input lines, a group of transistors whose gates are connected to a selected input line and whose source-drain paths are connected between the selected output line and a power supply potential; means for precharging each output line to a ground potential; means for precharging each input line to the power supply potential during the precharge period to turn off each transistor; and supplying an input signal to the input line during the sampling period. A logic array comprising means for supplying.