JP3281208B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a word line selection circuit for selectively driving a word line.

[0002]

2. Description of the Related Art As semiconductor memory devices become more highly integrated, there is an increasing demand for lowering the power supply voltage VCC and increasing the reading speed. FIG. 21 is a block diagram of a conventional word line selection circuit. In FIG. 21, a P-channel MO
The boosted potential VPP is supplied to the source of the S transistor (PMOSFET). The boosted potential VPP is a potential higher than a power supply voltage (VCC) externally applied. The boosted potential VPP is generally generated using a boosted potential generation circuit (not shown) provided inside the chip. N-channel MOS transistor (NMOSFET)
Are supplied with the ground potential VSS. P-channel MOS transistor drain and N-channel M
A word line WL connected to the memory cell is connected to the drain of the OS transistor. P channel MOS
The gate of the transistor and the gate of the N-channel MOS transistor are commonly connected, and a row decoder supplied with a power supply voltage VCC as a power supply is connected via a level conversion circuit. The row decoder is controlled by a control signal such as an address signal or a precharge signal, and selectively outputs a VC signal according to the signal level of the control signal.
C system output signal (H level is VCC level output signal)
Outputs _SVCC . The output signal of the VCC system is converted into a VPP system signal (H level VPP level signal) S _VPP by a level conversion circuit, and the converted signal is converted to a gate of a P-channel MOS transistor and a gate of an N-channel MOS transistor. Is supplied to

In the prior art disclosed in FIG. 21, a PMOSFET for driving a word line is provided between a word line and a boosted potential VPP. This PMOSFE
T is used in place of the bootstrap circuit used in a normal word line selection circuit. The bootstrap circuit includes an NMO for driving a word line in order to reduce a power supply voltage and to speed up a time for selecting a word line.
It consists of an SFET and an isolation transistor.

As described above, when a PMOSFET is used instead of the bootstrap circuit, the control signal input to the gate of the PMOSFET is a VPP control signal (H level is V
Control signal that is a PP). Because V
CC control signal (control signal whose H level is VCC)
This is because, when the PMOSFET is controlled by the above, when the H level (VCC) is input to the gate, the source voltage is VPP, so that the PMOSFET is not completely turned off. Therefore, the signal for controlling the gate of the PMOSFET needs to be a VPP control signal, but since the output of the row decoder is a VCC control signal, it is necessary to convert the signal level from the VCC level to the VPP level. is there. Therefore, the row decoder and P
It is necessary to provide a level conversion circuit between the MOSFET and the MOSFET.

[0005] This type of storage device is, for example, USPate.
nt Number 4,344,005. In addition, U.
S. Patent Number 4,344,005 discloses a word line killer circuit in addition to a level conversion circuit. When a boosted potential is supplied to a certain word line, the word line killer circuit sets another word line to the ground potential. The word line killer circuit is driven by a killer drive circuit. This killer drive circuit has a boosted potential VP like the level conversion circuit.
Let P be the power supply.

FIG. 22 is a circuit diagram of another conventional word line selection circuit. In FIG. 22, the PMOSFET corresponding to the level conversion circuit, which is provided in the row decoder portion of each word line selection circuit and whose gate is cross-coupled, is connected (see a broken line frame LS).

[0007] This type of storage device is, for example, an IEEE JOU.
RNAL OF SOLID-STATE CIRCUITS, VOL.26. NO.8, AUGUST
1991, pages 1171 to 1175. Also,
Japanese Patent Application Laid-Open No. 4-106794 discloses an EPROM. In the EPROM disclosed here, each of the address signal groups is level-converted and then input to the row decoder.

[0008]

These prior arts have the following problems. First, the storage devices shown in FIGS. 21 and 22 require many level conversion circuits. This is because a level conversion circuit must be provided for each of the word line selection circuits. For example, FIG.
In the technique shown in FIG. 22 and FIG. 22, the level conversion circuits are required for the number of word lines.

Similarly, even in a storage device which converts the level of each address signal group and then inputs it to a row decoder,
Many level conversion circuits are required. This is because a level conversion circuit must be provided for each of the address signal lines.

As the number of level conversion circuits increases, the chip area increases. At the same time, since the level conversion circuit uses the boosted potential VPP as a power supply, the consumption of the boosted potential VPP increases.

Second, the consumption of the boosted potential VPP increases even when a large number of circuits using the boosted potential VPP as power sources exist in the chip other than the level conversion circuit. Boost potential V
When the consumption of PP increases, the potential of the boosted potential VPP tends to fluctuate. In particular, the level of boosted potential VPP tends to decrease. In order to suppress the fluctuation of the boosted potential VPP, a sufficient boosted potential VPP must be supplied to the boosted potential wiring. In order to supply a sufficient boosted potential VPP to the boosted potential wiring, the area of the boosting capacitor of the boosted potential generating circuit must be increased. As the area of the boosting capacitor increases, the chip area increases.

Third, the level conversion circuit must be arranged near the memory cell array on the chip layout. The memory cell array generates noise. The level conversion circuit may malfunction due to the noise. As the integration density of the memory increases, the memory cell array generates larger noise. Therefore,
In a dynamic RAM of 64 megabits or 256 megabits or more, there is a high possibility that the level conversion circuit malfunctions. The present invention has been made in view of the second point, and an object of the present invention is to provide a semiconductor memory device that consumes less boosted potential.

[0013]

In order to achieve the above object, in a semiconductor memory device according to the present invention, a first output circuit for outputting a signal for driving a word line drive circuit and a word line noise killer circuit are provided. A word line driving signal line selection circuit including a second output circuit for outputting a driving signal, the first output circuit being operated at a potential difference between a boosted potential and a low potential, and It is characterized by operating with a potential difference between a high potential and a low potential instead of the boosted potential.

[0014]

According to the semiconductor memory device having the above configuration, the second output circuit is operated with the potential difference between the high potential and the low potential, so that the second output circuit does not consume the boosted potential.
Therefore, the semiconductor memory device consumes less boosted potential. This effect increases as the storage capacity increases and the number of drive signal line selection circuits increases.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. In this description, the same portions are denoted by the same reference symbols throughout the drawings, and redundant description will be avoided.

The present invention also relates to various semiconductor memory devices such as a dynamic RAM and a static RA.
M, rewritable ROM (EPROM), mask RO
However, the present invention has a configuration particularly suitable for a dynamic RAM, so that the following description will be made by taking a dynamic RAM as an example.

FIG. 1 is a block diagram of a VPP generation circuit, a level conversion circuit, a word line selection circuit, and a memory cell array included in a dynamic RAM according to a first embodiment of the present invention.

As shown in FIG. 1, a plurality of word lines WL0
To WLn are connected to a memory cell 10 and word line selection circuits 16-0 to 16-n, respectively. Each of the word line selection circuits 16-0 to 16-n is connected to the ground potential VSS.
And a row decoder (hereinafter referred to as a VPP row decoder) 13 to which VPP which is a boosted potential is supplied as a power source.
(13-0 to 13-n), boosted potential supply circuit (hereinafter referred to as VPP
And a word line drive circuit 11 (11-0 to 11-n).

Further, each of the word line driving circuits 11-0 to 11-n is a P-channel MOSFET (hereinafter referred to as PMOSF).
ET) 23 (23-0 to 23-n). P
The drains of the MOSs 23-0 to 23-n are connected to the word lines WL0 to WL0.
WLn. PMOS23-0-2
The source of 3-n is supplied with the boosted potential VPP via the VPP supply circuits 12-0 to 12-n. Boost potential VPP
Is a boosted potential higher than the power supply voltage VCC supplied from the external terminal. The boosted potential VPP is generated by a VPP generation circuit 14 provided inside the chip.

The VPP supply circuits 12-0 to 12-n respectively supply boosted potential V to the sources of the PMOSs 23-0 to 23-n.
This is for supplying PP, and may be, for example, a simple wiring. When the VPP supply circuits 12-0 to 12-n are wirings, the sources of the PMOSs 23-0 to 23-n are always supplied with the boosted potential VPP.

The VPP supply circuits 12-0 to 12-n
It may be included in a switching transistor. VP
When the P supply circuits 12-0 to 12-n include a switching transistor, if the output of the partial decoder is connected to the gate of the switching transistor, the switching transistor is turned on only when selected by the partial decoder, PMOS23-0 connected to it
VPP will be supplied to .about.23-n sources.

The gates of the PMOSs 23-0 to 23-n are controlled by signals corresponding to the output signals of the VPP row decoders 13-0 to 13-n, respectively. Here, the signals corresponding to the output signals are the row decoders 13-0 to 13-n and the PMO.
This is because there may be a circuit element such as an inverter between the gates of S23-0 to S23-n. The VPP row decoders 13-0 to 13-n are controlled by control signals such as a precharge signal and an address signal.

In the present invention, some of the control signals are VPP control signals (H level is VPP level).
Is important. Then, the VPP control signal is supplied to the VCC control signal (H
This is a signal whose level has been converted to VCC level.

In the dynamic RAM shown in FIG. 1, a certain VCC control signal is supplied to the VP by the level conversion circuit 15.
The level is converted to a P control signal. The converted signal is commonly input to a plurality of VPP row decoders 13-0 to 13-n. Therefore, unlike the circuits shown in FIGS. 21 and 22, there is no need to provide a level conversion circuit 15 for each word line selection circuit 16, and one level conversion circuit 15 is provided for a plurality of word line selection circuits 16. It can be provided. Therefore, the number of level conversion circuits 15 can be reduced, the chip area can be reduced, and power consumption can be further reduced.

In the dynamic RAM shown in FIG. 1, unlike the dynamic RAM shown in FIG. 21 and FIG.
Not provided every time. For this reason, the circuit 15 can be arranged away from the memory cell array that generates noise, and the level conversion circuit 15 can be not affected by noise generated from the memory cell array. As the integration density of the memory increases, the memory cell array generates larger noise. Especially 64 megabits or 25
With a large capacity dynamic RAM of 6 megabits or more,
Although noise generated in the memory cell array becomes relatively large as compared with a small-capacity dynamic RAM, malfunction of the circuit 15 is suppressed because the level conversion circuit 15 is far from the memory cell array. By suppressing the malfunction of the circuit 15, the dynamic RAM can operate stably.

On the other hand, in the dynamic RAM shown in FIGS. 21 and 22, since the level conversion circuit 15 is provided for each word line selection circuit 16, the circuit 15 is located near the memory cell array that generates noise. Must be placed in Therefore, 64 megabits, or 2
In a large-capacity dynamic RAM of 56 megabits or more, there is a high possibility that the circuit 15 malfunctions and cannot operate stably.

In the dynamic RAM shown in FIG. 1, however, if the level conversion circuit 15 and the word line selection circuit 16 are too far apart, the influence of noise is less likely to occur, but the length of the wiring connecting them is long. Therefore, there is a disadvantage that the parasitic capacitance of the connection wiring is increased and the circuit operation is delayed. Therefore, as a layout of the circuit portion on the chip layout, a region (memory cell array) where a memory cell is formed adjacent to one side of a region where the word line selection circuit 16 is formed on the semiconductor substrate is arranged (this Is to reduce the wiring length of the word line as much as possible in order to prevent an increase in the parasitic capacitance of the word line.) Another side (preferably opposite to the region where the memory cell is formed) It is desirable to arrange a region where the level conversion circuit 15 is formed adjacent to the word line selection circuit 16). For example, a region where the word line selection circuit 16 is formed is arranged between a region where the level conversion circuit 15 is formed and a region where the memory cell is formed. With such a configuration, the level conversion circuit 15 is separated from the memory cell array by an area in which the word line selection circuit 16 is formed, and the effect of noise generated in the memory cell array can be sufficiently prevented. In addition, since it is possible to prevent the wiring length of the wiring connecting the level conversion circuit 15 and the word line selection circuit 16 from becoming long, wiring delay hardly causes a problem. It is also effective in that the chip size can be reduced.

Although the boosted control signal is used for controlling the row decoder 13 in the first embodiment, the word line selection circuit in an actual product has various functions other than the row decoder. Since there are circuit portions (for example, a circuit relating to redundancy), a boosted control signal may be used for those portions as well. Therefore, the present invention is not limited to the one related to the control signal for controlling the row decoder as in the above embodiment, but is applied to many signals for controlling the word line selection circuit within a range in which the purpose and effect can be obtained. It is possible.

Next, the dynamic RAM according to the first embodiment includes a VPP generation circuit, a level conversion circuit,
Specific circuit configurations of the word line selection circuit and the memory cell will be described.

FIG. 2 is a specific circuit diagram of the word line selection circuit shown in FIG. 1, FIG. 3 is a specific circuit diagram of the level conversion circuit shown in FIG. 1, and FIG. 4 is a VPP generation circuit shown in FIG. It is a circuit diagram of a circuit.

First, as shown in FIG. 2, a memory cell 10 is connected to each of a plurality of word lines WL0 to WLn. The memory cell 10 includes one transistor 2
Dynamic RA including one and one capacitor 22
M cell. The word line WL is connected to the PMOSFET 23
(23-0 to 23-n) and NMOSFET 24 (24-0 to 2)
4-n) and the word line driving circuit 11 (11-0 to 11-
n) is connected to. The drain of the PMOSFET 23 is connected to the drain of the NMOSFET 24, and the source thereof is supplied with the boosted potential VPP. NMOSFE
The ground potential VSS is supplied to the source of T24. In this embodiment, the VPP supply circuit 12 (12-0
To 12-n) correspond to the wiring connecting the source of the PMOSFET 23 and the boosted potential VPP. PMOSFET2
The gate of the NMOSFET 3 and the gate of the NMOSFET 24 are commonly connected to each other, and this common connection point is connected to the output node a of the VPP row decoder 13 (13-0 to 13-n). This VPP-related row decoder 13 has a boosted potential VP
PMO for precharge between P and ground potential VSS
The configuration includes an SFET 26 (26-0 to 26-n) and a decode circuit unit 29 (29-0 to 29-n) composed of a NAND gate connected in series. VPP row decoder 1
Reference numeral 3 is controlled by address signals A0 to Ak, / A0 to / Ak (the leading / is a "bar" and indicates an inverted signal) and a precharge signal PRCH '. The precharge signal PRCH 'is a VPP-based control signal.
This is a signal whose level has been converted. The output node a of the VPP row decoder 13 has a noise killer circuit 17 (17-0) for preventing a change in the potential level of the output node a.
To 17-n) are connected. Noise killer circuit 17
Is a load PMOSFET 28 whose source is supplied with the boosted potential VPP and whose drain is connected to the output node a.
(28-0 to 28-n), the boosted potential VPP is used as a power source,
Inverter 30 (30-0 to 30-3) that supplies an inverted level of the potential level of output node a to the gate of MOSFET 28.
0-n).

FIG. 4 is a specific circuit diagram of a boosted potential generating circuit for generating boosted potential VPP. As shown in FIG. 4, the boosted potential generating circuit 14
0, means for generating complementary first and second clock signals CP1 and CP2 by the inverter 31, a first boosting capacitor 32 to which one end of the first clock signal CP1 is supplied, and a power supply voltage VCC. Is connected between the terminal to which the second clock signal CP2 is supplied and the first MOSF connected between the terminal to which the second clock signal CP2 is supplied.
ET33, a terminal to which the power supply voltage VCC is supplied, and the second boosting capacitor 35, and the first gate is connected to the gate.
Second MOSFET to which the clock signal CP1 is supplied
And a MOSFET whose drain and gate are commonly connected to a node between the first MOSFET 33 and the boosting capacitor 32, and whose source is connected to the boosted potential output terminal 38.
24, a drain and a gate commonly connected to a connection node between the second MOSFET 34 and the second boosting capacitor 35, and a source connected to a boosted potential output terminal 38.
OSFET 27.

Such a boosted potential generating circuit 15 is connected to the DR
The boosted potential VPP generated by this circuit is generally supplied to a word line selection circuit 16 via a power supply line.

Next, the operation of the circuit having the configuration shown in FIG. 2 will be described. Row address signals A0 to Ak, / A0 to
Before inputting / Ak to the NAND gate 29, a precharge signal PRCH ', which is a control signal of the VPP system, is set to a high level, a low level,
Higher level order (ie, VPP level, VSS level,
VPP level). PMOSFET 26
Turns on when the signal PRCH 'is at the VSS level, and turns off after the output node a is charged to the VPP level.

The load PMOSFET 28 is a PMOS
This is provided to prevent the potential level of the output node a from fluctuating due to noise or the like when the FET 26 is turned off and the output node a temporarily enters a floating state. Here, the inverter 30 whose output terminal is connected to the gate of the PMOSFET 28 outputs the boosted potential VPP.
And a ground potential VSS.
Includes SFET and NMOSFET. Inverter 30
However, the reason why the boosted potential VPP is used as the power supply is as follows. When the potential VCC is used as the power supply instead of the boosted potential VPP, the PMOSFET constituting the inverter does not turn off completely when the output node a is at the H level. For this reason, the operation of the inverter becomes unstable, which hinders the speeding up of the word line.

After the elapse of the predetermined period as the precharge operation, the address signals A0 to Ak, / A0 to / Ak
Are input to the NAND gate 29.
Considering the word line selection circuit 16 connected to the selected word line WL, only the output node a corresponding to the selected word line goes to the VSS level, and the PMOSFE
T23 turns on and NMOSFET 24 turns off. As a result, the selected word line WL goes to the VPP level,
The transistor 21 of the memory cell 10 connected to the word line WL is turned on, and the data stored in the capacitor 22 is transferred to the bit line BL. In this case, the output node a in the word line selection circuit 16 corresponding to the unselected word line WL remains at the VPP level. Therefore, the PMOSFET 23 is turned off and the NMOSFET 24 is turned on, so that the VPP level potential is not supplied to the unselected word line WL, so that data is not read from the memory cell 10.

Here, the NMOSFET 24 turns on when the word line WL is not selected, and sets the potential of the word line WL to 0.
This is provided to fix the level to the level, thereby preventing the word line WL from being in a floating state. This is effective in preventing the potential of the word line WL from fluctuating due to the influence of noise and preventing an unselected word line WL from being selected.

In this embodiment, among the signals for controlling the row decoder 13 of the VPP system, the PMOSFET 26
Control signal PR supplied to the gate of
The level conversion is performed only for the CH, and the VPP control signal PR
CH ′. NM constituting NAND gate 29
The address control signals A0 to Ak and / A0 to / Ak supplied to the gate of the OSFET remain the VCC control signals. This is because the control signal for controlling the PMOSFET must necessarily be a VPP-based control signal.
This is because the control signal for controlling the MOSFET does not necessarily need to supply a VPP-based control signal. That is, when the PMOSFET is controlled by the control signal of the VCC system, the transistor is not completely turned off when the control signal is at the H level (VCC level).
In the OSFET, when the control signal of the VCC system is at the L level (VS
This is because the transistor is completely turned off at (S level), so that no inconvenience occurs in the circuit operation. In addition, NMOSF
Even if the ET control signal is a VPP-based control signal, there is no problem in circuit operation.

For the above reasons, the word line selection circuit 16
Is not a problem in circuit operation even if all the control signals are VPP-based control signals.
The control signal supplied to the ET needs to be a VPP control signal. In this embodiment, a PMOSFET 26 is used as a transistor for precharging. The use of a PMOSFET for the transistor for precharging is more effective than the case where an NMOSFET is used, because it has the effect of preventing a threshold drop.

It should be noted that in the first embodiment, one or more signals (at least the PMOS
It is important to use a VPP-based control signal for the FET control signal). It does not matter how the VPP control signal is generated.

In the first embodiment, the control signal PRCH, which is a precharge signal, is changed from the VPP control signal PRCH.
One level conversion circuit 27 is used for level conversion to CH '.

As described above, in the first embodiment, since it is not necessary to provide a level conversion circuit for each of a plurality of row decoders, the number of level conversion circuits is reduced. In addition, the number of level conversion circuits is reduced as compared with a storage device which inputs the address signal group to the row decoder after the level conversion.

Therefore, in the dynamic RAM, an increase in the chip area is suppressed, and the consumption of the boosted potential VPP is reduced. Further, in a storage device that performs level conversion of each address signal group, it takes time until the address signal group is input to the row decoder, and particularly, speeding up of a word line selection operation is prevented. In the first embodiment having the configuration, the speeding up of the word line selecting operation is not particularly hindered. The precharge signal is
This is because the precharge of the row decoder and the precharge are only released.

Further, if the memory cell array and the level conversion circuit are arranged apart from each other, the dynamic RAM hardly malfunctions. Further, in the first embodiment, the power supplied to the word line selection circuit is two, that is, the boosted potential VPP and the ground potential VSS, and the potential VCC is not required. That is, the power supply lines led to the circuit area where the word line selection circuit is formed on the chip are the VSS line and the VPP
Only two power lines are required and no VCC line is required. Therefore, one power line (VSS line and VPP line)
Can be designed to be sufficiently thick. By increasing the width of the power supply line, it is possible to prevent the potential level of the power supply line from fluctuating due to noise or the like. There is also an advantage that circuit design becomes easy.

In the first embodiment, the output node a of the VPP-based row decoder 13 is directly connected to the gates of the PMOSFET 23 and the NMOSFET 24 in the word line drive circuit. However, a plurality of VPP-based inverters are provided. It is obvious that they may be connected indirectly, and the same applies to the following embodiments.

FIG. 5 is a circuit diagram showing a modified example of the word line selection circuit particularly described with reference to FIG. The difference between the word line selection circuit according to the modification shown in FIG. 5 and the word line selection circuit shown in FIG.
−0) and the gate of the PMOSFET 23 of the word line drive circuit 11 (only 11-0 is shown) without being directly connected to the row decoder 13 and the word line drive circuit 1.
1, a VPP system inverter 18 (only 18-0 is shown) and a VPP system inverter 19 (only 19-0 is shown) are inserted. Inverter 1
Reference numerals 8 and 19 are provided to control timing for controlling the PMOSFET 23.

The output node a of the row decoder 13
And the gate of the PMOSFET 23 of the word line drive circuit 11 via the inverters 18 and 19, the waveform of the output signal of the row decoder 13 can be adjusted by the inverters 18 and 19. Therefore, a signal in which the “H” level and the “L” level are clearly distinguished is
The signal is input to the gate of the PMOSFET 23 of the word line drive circuit 11, which is useful for speeding up operation and preventing malfunction due to erroneous detection of a signal level.

As shown in FIG. 2, the row decoder 13 and the word line drive circuit 11 are not only directly connected to each other, but also indirectly connected via an inverter or the like as shown in FIG. May be. In short, the word line driving PMOSFET 23 and the NMOSFET 24 may be controlled according to the potential level of the output node a of the row decoder 13.

Next, a dynamic RAM according to a second embodiment of the present invention will be described. FIG. 6 is a block diagram of a VPP generation circuit, a level conversion circuit, a word line selection circuit, and a memory cell array included in the dynamic RAM according to the second embodiment of the present invention.

In particular, as shown in FIG. 1, in the dynamic RAM according to the first embodiment, the word line driving circuit 11
VPP supply circuits 12-0 to 12-n are provided for each of -0 to 11-n. This is, as shown in FIG.
The supply circuit 12 includes a plurality of word line drive circuits 11-0 to 11
-n may be shared.

In the dynamic RAMs according to the first and second embodiments, one level conversion circuit is used to convert the level of the precharge signal. Conversion circuits may be provided in parallel. The reason why a plurality of circuits that operate exactly the same for one control signal is provided is because, for example, the parasitic capacitance of the wiring length and the driving capability of the level conversion circuit are considered. For example, when a memory cell is divided into several blocks, a plurality of level conversion circuits may be provided in parallel for each block or for some blocks. This can be similarly applied to a plurality of embodiments described below.

Next, a dynamic RAM according to a third embodiment of the present invention will be described. FIG. 7 is a block diagram of a level conversion circuit, a word line selection circuit, and a VPP supply circuit included in the dynamic RAM according to the third embodiment of the present invention.

The dynamic RAM according to the third embodiment shown in FIG. 7 relates to a partial decode dynamic RAM. The partial decoding method has an advantage that low voltage operation is possible because the number of transistors connected in series between power supply potentials can be reduced.
From such advantages, the partial decoding method is suitable for a large-capacity dynamic RAM.

Dynamic RAM according to Third Embodiment
However, the difference from the dynamic RAM according to the first embodiment shown in FIG. 1 or the dynamic RAM according to the second embodiment shown in FIG. (Generally called partial decoding, and also sometimes called predecoding).

Dynamic RAM according to Third Embodiment
Is provided with a partial decoder 40.
(40a to 40d) are shown in FIG. A plurality of partial decoders 40 are provided. In the embodiment shown in FIG. 7, four partial decoders 40a to 40d
Is provided. Four partial decoders 40a-
A signal obtained by converting the second control signal of the VCC level to the VPP level by the second level conversion circuit 15-2 is supplied to 40d. Four partial decoders 40a
To 40d output word line drive signals WDRV1 to WDRV4 at the VPP level, respectively. The word line drive signals WDRV1 to WDRV4 are supplied to the word line selection circuit 16A.
(16A-0 to 16A-n). The word line selection circuit 16A is slightly modified compared to the first and second embodiments due to the provision of the plurality of partial decoders 40. Specifically, a word line drive circuit 11 is provided for each of the word line drive signals WDRV1 to WDRV4.

In the embodiment shown in FIG. 7, word line drive signals WDRV1 to WDRV1 to WD are provided in one word line selection circuit 16A.
Four word line drive circuits 11a to 11d are provided for each RV4. The word line drive circuit 11a connects the gate to the output node a of the main row decoder 13,
A PMOS having a source connected to the output node b of the partial decoder 40a and a drain connected to the word line WL1
FET 23a is included. Similarly, the word line drive circuit 11b
Is a gate connected to the output node a of the main row decoder 13.
And a PMOSFET 23b having a source connected to the output node b of the partial decoder 40b and a drain connected to the word line WL2. Similarly, the word line drive circuit 11c connects the gate to the output node a of the main row decoder 13 and connects the source to the partial decoder 4
0c, and the drain is connected to the word line WL.
3 includes a PMOSFET 23c. Similarly, the word line drive circuit 11d includes a PMOSFET 23d having a gate connected to the output node a of the main row decoder 13, a source connected to the output node b of the partial decoder 40d, and a drain connected to the word line WL4. .

In the dynamic RAM of the partial decoding system, a plurality of word line selection circuits 16A having the above configuration are provided. In the embodiment shown in FIG. 7, word line selection circuits 16A-0 to 16A-n are provided. Each of the word line selection circuits 16A-0 to 16A-n includes one main row decoder 13. Main row decoders 13-0 to 13-n
In the same manner as in the first and second embodiments, the first control signal of the VCC level is converted by the first level conversion circuit 15-1.
A signal converted to the VPP level is supplied.

When the dynamic RAM of the partial decode system is realized by using a conventionally known technique, for example, the word line selection circuit 16A (16A-0 to 16A) is used.
A-n) and the partial decoder 40 (40a to 40a).
It was necessary to provide a level conversion circuit inside each of 40d). As a result, the number of circuits has increased, and the number of transistors has also increased.

However, in the dynamic RAM according to the third embodiment, the first control signal is level-converted.
A level conversion circuit 15-1 for the main row decoder;
And a level conversion circuit 15-2 for a partial decoder, which converts the level of the control signal, is provided, and the number of circuits is reduced. Thereby, the number of transistors is greatly reduced. Therefore, both the dynamic RAM according to the third embodiment and the dynamic RAMs according to the first and second embodiments are effective in reducing the circuit area, and can achieve the object of increasing the integration density. . Further, since the number of level conversion circuits is reduced, the consumption of the boosted potential VPP can be reduced.

The third embodiment has the following effects in addition to the above effects. Conventional dynamic type R
AM has a word line driving circuit and a word line driving NMO.
SFET and isolation MOSF for suppressing backflow of carriers charged to the gate of drive NMOSFET
Some use a bootstrap circuit composed of ET. In this case, in order to prevent the threshold value of the driving NMOSFET from dropping, first, the output of the main row decoder is determined, and after sufficiently charging the gate of the driving NMOSFET, the output of the partial decoder (word line driving) is obtained. There is a limitation on the timing of applying a signal (signal WDRV) to the source of the driving NMOSFET to couple the gate and source of the driving NMOSFET. Because of this timing limitation, the word line drive signal WDRV
Must be delayed, and the word line selection time will be delayed.

However, as in the third embodiment, the PMOS
If an FET is used as a transistor for driving a word line, it is not necessary to consider a drop in threshold voltage. For this reason, the timing limitation is eliminated. That is, it is not necessary to apply the precharge signal PRCH2 'of the partial decoder after a predetermined time has elapsed after the application of the precharge signal PRCH1' of the main row decoder. May be provided to the main decoder and the partial decoder at the timing described above. When the P-channel MOS transistor is used as the driving transistor in this manner, the control timing of the main decoder and the partial decoder is not limited in the partial decoding method, so that there is an effect that the word line can be selected faster than in the past. .

Next, a dynamic RAM according to a fourth embodiment of the present invention will be described. The dynamic RAM according to the fourth embodiment is a more specific example of the dynamic RAM according to the third embodiment shown in FIG.

FIG. 8 is a block diagram schematically showing a configuration of a dynamic RAM according to a fourth embodiment of the present invention. As shown in FIG. 8, the precharge signal generation circuit 1 generates a VCC level precharge signal PRCH used for precharging and releasing the main row decoder and the partial decoder. The VCC level precharge signal PRCH is supplied to the level conversion circuit 15.
The first precharge signal PRCH1 at the VPP level
'And the second precharge signal PRC at the VPP level
The level is converted to H2 '. The level-converted precharge signals PRCH1 ′ and PRCH2 ′ may be directly input to the main row decoder and the partial decoder, but are input to the main row decoder and the partial decoder via a buffer circuit including an inverter circuit. You may. This is the precharge signal PRC
When the timings of H1 'and PRCH2' are shifted from each other, or when the precharge signals PRCH1 'and PRCH2'
This is performed when necessary, for example, when changing the current driving capabilities of CH2 '.

Eight main row decoders 13 are provided. Each of the eight main row decoders 13-0 to 13-7 has a level-converted first precharge signal P
RCH1 'is commonly input. Main row decoder 1
The number of row address signals input to 3-0 to 13-7 is "A
3 "," A4 "," A5 "," / A3 "," / A4 "and" / A5 "Eight combinations of signals are obtained from the six row address signals. Each of the eight combinations of signals corresponds to the main row decoder 13.
-0 to 13-7 are input.

Eight word line selection circuits 16A are provided. The eight word line selection circuits 16A-0 to 16A-7 each include one main row decoder 13, an output line a connected to the output of the main row decoder 13, and four output lines a connected to the output line a. Divided output wirings aa to ad,
Word line driving circuits 11a to 11d provided one for each of divided output wirings aa to ad, and word line noise killer circuits 41a to 41d provided for four word lines WL are included.

A word line drive signal line selection circuit 39 including a partial decoder 40 is provided. In this embodiment, four word line drive signal line selection circuits 39a to 39a to
39d are provided. Partial decoder 40a-
The level-converted second precharge signal PRCH2 'is commonly input to each of 40d. The row address signals input to the partial decoders 40a to 40d are "A0", "A1", "/ A0" and "/ A1".
Are four in total. Four combinations of signals are obtained from the four row address signals. Each of the four combinations of signals is input to the partial decoders 40a to 40d.

In this embodiment, four row address signals are input to the partial decoder. If the number of row address signals is six, eight combinations of signals can be obtained.
At this time, eight partial decoders 40 are provided,
The number of divided output lines provided in the word line selection circuit 16A is also changed from four to eight.

The word line drive signal line selection circuit 39a is connected to a pair of word line drive signal lines. A pair of words
Of the word line drive signal lines, one of the word line drive signals WDR
At the intersection of V and the divided output wiring aa of the main row decoders 13-0 to 13-7, word line driving circuits 11a-0 to 11a
-7 is provided. Another word line drive circuit 11b (1
1b-0 to 11b-7) to 11d (11d-0 to 11d-7), respectively, as shown in FIG.
It has the same configuration as a. Also, of the pair of word line drive signal lines, the other inverted word line drive signal line / WDRV
And word line noise killer circuits 41a-0 to 41-41 at the intersections of the main row decoders 13-0 to 13-7.
a-7 is provided. Other word line noise killer circuits 41b (41b-0 to 41b-7) to 41d (41d-0 to 4d)
1d-7) have the same configuration as the word line noise killer circuit 41a, as shown in FIG.

FIG. 9 is a circuit diagram of the word line selection circuit shown in FIG. As shown in FIG.
The circuit of A-0 is almost the same as the circuit shown in FIG. The most different point is that one output wiring a is connected to four divided output wirings aa to ad. Word line drive circuits 11a-0 to 11d-0 are also substantially the same as the circuit shown in FIG. However, PMOSFETs 23a-0 to 23
The source of d-0 has a word line drive signal W of VPP level.
DRV1 to WDRV4 are supplied.
The word line drive circuits 11a-0 to 11d-0 are turned on by being supplied with the word line drive signals WDRV1 to WDRV4. Outputs of the word line driving circuits 11a-0 to 11d-0 are connected to word lines WL1 to WL4. Word line W
L1 to WL4 include a word line noise killer circuit 41a-0.
To 41d-0 are connected. The word line noise killer circuits 41a-0 to 41d-0 each have a source connected to the low potential power supply line VSS and a drain connected to the word lines WL1 to WL4.
, And NMOSFETs 42a-0 to 42d-0.
The inverted word line drive signals / WDRV1 to / WDRV4 are input to the gates of the NMOSFETs 42a-0 to 42d-0. The NMOSFETs 42a-0 to 42d-0 are turned on when the inverted word line drive signals / WDRV1 to / WDRV4 are at "H" level, and set the potentials of the word lines WL1 to WL4 to V
SS level. Word line noise killer circuit 41a-0
To 41d-0 are not connected to the word line, the output of the main row decoder and the word line drive signal WDR
When V is at the “L” level, the potential of the word line WL is at the “L” level. However, the potential of the word line actually varies between 0 V and the threshold value Vth due to noise or the like. For this reason, a malfunction may occur. Therefore, the inverted word line drive signals / WDRV1 to / WDRV
DRV4 is at "H" level, that is, the word line drive signal WDR
NM that turns on when V1 to WDRV4 are at "L" level
By providing the word line noise killer circuits 41a-0 to 41d-0 including the OSFETs 42a-0 to 42d-0, the potential of the word line WL can be fixed at the VSS level, and the fluctuation of the potential of the word line is suppressed. Is done. The inverted word line drive signals / WDRV1 to / WDRV4 are the same as the drive word line drive signals WDRV1 to WDRV4,
Level may be used, but in the fourth embodiment, VCC
Level.

Although not shown, the other word line selection circuits 16A-1 to 16A-7 are similar to the word line selection circuit 16A-0 shown in FIG. FIG. 10 is a circuit diagram of the word line drive signal line selection circuit shown in FIG.

As shown in FIG. 10, the word line drive line signal line selection circuit 39a includes a partial decoder 40a. The partial decoder 40a has the same configuration as the main row decoder 13-0 shown in FIG. The output wiring c of the partial decoder 40a is connected to the word line driving signal line driving circuit 43a. The output wiring c has
A noise killer circuit 44a having the same configuration as the noise killer circuit 17-0 shown in FIG. 2 is connected.

The drive signal line drive circuit 43a has a PMOSFET in which the source is connected to the boosted potential power supply line VPP, the drain is connected to the output line b, and the gate is connected to the output line c.
45a and an NMOSFET 46a having a source connected to the low potential power supply line VSS, a drain connected to the output wiring b, and a gate connected to the output wiring c. The drive signal WDRV1 is extracted from the output wiring b.

A killer drive circuit 47a for driving the word line noise killer circuit is connected to the output wiring b.
Killer drive circuit 47a includes an inverter to generate inverted signal / WDRV1 of drive signal WDRV1. The killer drive circuit 47a has a PMOSFET 48a having a source connected to the high potential power supply line VCC, a drain connected to the output wiring d, a gate connected to the output wiring b, a source connected to the low potential power supply line VSS, and a drain connected to the low potential power supply line VSS. NMOSFET 49 connected to output wiring d and gate connected to output wiring b
a. From the output wiring d, the inverted drive signal / WDR
V1 is extracted. The killer drive circuit 47a may include an inverter supplied with the boosted potential VPP as a power supply, or may include an inverter supplied with a high potential VCC as a power supply as shown in FIG.

When the killer drive circuit 47a includes an inverter supplied with the boosted potential VPP as a power supply,
Since the potential of the word line can be quickly set to the VSS level, the speed can be increased, and advantages such as elimination of the VCC line are obtained.

On the other hand, high potential VC is applied to killer drive circuit 47a.
When an inverter supplied with C as a power supply is included, advantages such as a reduction in consumption of the boosted potential VPP can be obtained.

In a large-capacity storage device, the boosted potential VP
The merit is greater if the consumption of P can be reduced.
If the consumption of the boosted potential VPP can be reduced, the boosted potential VPP
This is because there are effects such as the potential fluctuation of PP and the area of the boosting capacitor can be reduced.

Although not shown, the other word line drive line signal line selection circuits 39b to 39d are the same circuits as the word line selection circuit 16A-0 shown in FIG. In addition, the word line drive line signal line selection circuits 39a to 39d
In addition to the circuit shown in FIG. 5, the circuit shown in FIG.

Dynamic RAM According to Fourth Embodiment
Then, the precharge signal PRCH is level-converted, and the level-converted precharge signals PRCH1 ′, PRCH
Since 2 'is input to the main row decoder and the partial row decoder, the number of level conversion circuits can be reduced. In order to reduce the number of level conversion circuits, the number of transistors is reduced. Further, since the number of level conversion circuits can be reduced, the consumption of the boosted potential VPP is reduced.

A precharge signal PRCH1 'for precharging the main row decoder and a precharge signal PRCH for precharging the partial decoder are provided.
Since each of 2 ′ is produced using one level conversion circuit, the number of level conversion circuits can be further reduced.

Further, since the inverted drive signal / WDRV is generated by using an inverter using the high potential VCC as a power supply, the consumption of the boosted potential VPP can be further reduced. Next, a chip layout of the dynamic RAM according to the fourth embodiment will be described. The chip layout described below is a new and useful chip layout that can achieve high integration density, excellent workability, suppression of noise interference between circuits, and the like.

FIG. 11 is a diagram showing a chip layout of a dynamic RAM according to the fourth embodiment. FIG.
As shown in FIG. 1, there is a memory cell array 100 in which memory cells are arranged. The word line drive circuit array 101 includes PMOSFETs 23a-0 to
23a-7, 23b-0 to 23b-7, 23c-0 to 23c-7,
23d-0 to 23d-7, NMOSFET 24a-0 to 24a
-7, 24b-0 to 24b-7, 24c-0 to 24c-7, 24d
-0 to 24d-7 are arranged. A word line noise killer circuit array 102 is arranged between the memory cell array 100 and the word line drive circuit array 101. The word line noise killer circuit array 102 includes NMOSFETs 42a-0 to 42a-7 included in the word line noise killer circuit,
42a-0 to 42a-7, 42a-0 to 42a-7, 42a-0 to
42a-7 are arranged.

Word line drive signal line drive circuit array 103
Are arranged adjacent to the word line drive circuit array 101. In this layout, the word line drive signal drive circuit array 103 includes two drive signal line drive circuit arrays 1
03-1 and a drive signal line drive circuit array 103-2. The word line drive circuit array 101 includes the array 10
It is arranged between 3-1 and the array 103-2. The drive signal line drive circuit array 103-1 includes PMOSFETs 45a and 45c, an NMOSFET 45 included in the drive signal line drive circuit.
a and 45c are arranged. On the other hand, the drive signal line drive circuit array 103-2 includes a PMOS transistor included in the drive signal line drive circuit.
FET 45b, 45d, NMOSFET 45b, 45d
Is arranged.

The killer drive circuit array 104 is arranged adjacent to the word line noise killer circuit array 102. In this layout, the killer drive circuit array 104
Are divided into two killer drive circuit arrays 104-1 and a drive signal line drive circuit array 104-2. Word line noise killer circuit array 102 is arranged between arrays 104-1 and 104-2. The killer drive circuit array 104-1 includes a PMOSFET 4 included in the killer drive circuit.
8a, 48c and NMOSFETs 49a, 49c are arranged. On the other hand, the killer drive circuit array 104-2 includes PMOSFETs 48b, 48d, NM included in the killer drive circuit.
OSFETs 49b and 49d are arranged.

FIG. 12 is a diagram showing in detail the word line drive circuit array 101 and the word line noise killer circuit array 102 in the chip layout shown in FIG. 11, and FIG. Out of the chip layout shown in FIG.
FIG. 13B (b) shows the killer drive circuit array 104-1 in detail, and FIG. 13B (b) shows the drive signal drive circuit array 103-2 and the killer drive circuit array 104-2 in the chip layout shown in FIG. It is the figure which showed the part in detail.

As shown in FIG. 12, NMOSFETs 42a-0 to 42a-7, 42 included in the word line noise killer circuit
b-0 to 42b-7, 42c-0 to 42c-7, 42d-0 to 42
d-7 is a PMOSFET 23a included in the word line driving circuit.
-0 to 23a-7, 23b-0 to 23b-7, 23c-0 to 23c
-7, 23d-0 to 23d-7, NMOSFET 24a-0 to 2
4a-7, 24b-0 to 24b-7, 24c-0 to 24c-7, 2
4d-0 to 24d-7 are shifted by 90 degrees.
In FIG. 12, the direction of the current flowing through each MOSFET is indicated by an arrow. The direction of the arrow points in the gate length direction at the same time as the direction of the current.

As shown in FIGS. 13A and 13B, the PMO included in the word line driving signal line driving circuit
SFETs 45a to 45d, NMOSFETs 46a to 46
d is the NMOSFET included in the word line noise killer circuit
42a-0 to 42a-7, 42b-0 to 42b-7, 42c-0 to
42c-7 and 42d-0 to 42d-7 are arranged in the same direction. Similarly, the PMOSFE included in the killer drive circuit
T48a to 48d and NMOSFETs 49a to 49d
NMOSFET 42a included in the word line noise killer circuit
-0 to 42a-7, 42b-0 to 42b-7, 42c-0 to 42c
-7, 42d-0 to 42d-7 in the same direction. In FIGS. 13A and 13B, similarly to FIG. 12, the direction of the current flowing through each MOSFET is indicated by an arrow. The direction of the arrow points in the gate length direction at the same time as the direction of the current.

In the chip layout shown in FIG. 11, the memory cell array and the word line driving circuit array are separated from each other by disposing the word line noise killer circuit array between the memory cell array and the word line driving circuit array. Can be. For this reason, noise interference is suppressed between the memory cell array and the word line drive circuit array. By suppressing the noise interference, the possibility that the storage device malfunctions can be further reduced.

Further, FIG. 12, FIG. 13 (a) and FIG.
As shown in FIG. 3B, the NMOSFET included in the word line noise killer circuit and the PMO included in the word line driving circuit are included.
By arranging the SFET and the NMOSFET at a shift of 90 degrees, the area of the word line noise killer circuit array does not increase unnecessarily. That is, it has a high integration density. Further, the word line pattern can be formed so as to extend over the word line noise killer circuit array from the word line drive circuit to the memory cell array. That is, the word lines can be formed in a linear pattern.
A linear pattern can withstand fine processing as compared to a pattern that bends repeatedly. That is, it has excellent workability. FIG. 14 shows a pattern after the word lines are formed.

FIG. 15 is a pattern plan view of a memory cell array. As shown in FIG.
00, a memory cell 200 including one transfer transistor and one capacitor is integrated.
The transfer transistor is arranged to be shifted by 90 degrees from the NMOSFET included in the word line noise killer circuit. The memory cell 200 is a buried plate trench cell (hereinafter, referred to as a BPT cell) having a high integration density. FIG. 16 shows a cross-sectional view of the BPT cell 200.

As shown in FIG. 15, a capacitor 201 of a BPT cell 200 has a plate potential V from an N-type silicon layer 202 formed inside a P-type silicon substrate.
PL is provided. N-type silicon layer 202 is formed by N-type impurities diffused from the bottom of trench 203. Since the N-type silicon layer 202 is embedded in the substrate, it is also called an embedded wiring layer.

The chip layout shown in FIG. 11 can further obtain the following effects when the BPT cells 200 are integrated in the memory cell array. FIG. 17 is a schematic sectional view of a word line drive circuit array, a word line noise killer circuit array, and a memory cell array.

As shown in FIG. 17, the BPT cell 200
Has an N-type embedded wiring layer 202. The N-type buried wiring layer 202 has a plate potential VPL (normally, a power supply potential VC).
C) (about 1/2 of C). The word line drive circuit array has an N-type well as a region for forming a PMOSFET. The N-type well has a boosted potential VPP
Is supplied. If the N-type well to which the boosted potential VPP is supplied is arranged near the N-type buried wiring layer 202, the N-type buried wiring layer 2 is formed by the potential of the N-type well.
02 fluctuates.

However, as shown in FIG. 17, a word line noise killer circuit 102 is arranged between the memory cell array 100 and the word line drive circuit 101. The N-type well to which the boosted potential VPP is supplied and the N-type buried wiring layer 202 are separated from each other by the word line noise killer circuit 102. For this reason, the fluctuation of the potential of the N-type buried wiring layer 202 can be suppressed.

FIG. 18 is a diagram showing a chip layout of a block of the dynamic RAM according to the fourth embodiment shown in FIG. As shown in FIG. 18, a main row decoder array 105 in which a main row decoder is arranged includes
It is provided adjacent to the word line drive circuit array 101.
The partial decoder array 106 in which the partial decoder is arranged is divided into two arrays 106-1 and 106-2. The array 106-1 is provided adjacent to the word line drive signal line drive circuit array 103-1. On the other hand, the array 106-2 is provided adjacent to the word line drive signal line drive circuit array 103-2. The level conversion circuit area 107 in which the level conversion circuit is arranged is provided adjacent to the main row decoder array 105.

Further, the capacitor region 108 in which the boosting capacitor is arranged is provided in the main row decoder array 10.
5 are provided adjacent to each other. The booster circuit region 109 in which the booster circuit is arranged is provided adjacent to the capacitor region 108.

In the chip layout shown in FIG. 18, between the level conversion circuit area 107 and the memory cell array 100, the main row decoder array 105, the partial decoder array 106-2, the word line drive circuit array 101,
A word line noise killer circuit array 102 is provided.
Therefore, noise interference between the level conversion circuit and the memory cell array can be suppressed.

Further, since level conversion circuit region 107 is provided adjacent to main row decoder array 105, the distance from the level conversion circuit to the main row decoder can be reduced. For this reason, the length of the wiring connecting the level conversion circuit and the main row decoder can be shortened, and the signal delay caused by the wiring hardly causes a problem. Also, since the partial decoder arrays 106-1 and 106-2 are provided adjacent to the main row decoder array 105,
The distance from the level conversion circuit to the partial decoder is also reduced.

In an actual storage device, a plurality of memory blocks shown in FIG. 18 are integrated in one chip to realize a large-scale storage capacity. At this time, the capacitor region 108 and the booster circuit region 109 are provided for each memory block.
Are provided. In this manner, by providing the capacitor region 108 and the booster circuit region 109 for each memory block, the boosted potential VPP with small potential fluctuation can be generated. The fluctuation of the boosted potential VPP causes a malfunction of the circuit.

FIG. 19 is a circuit diagram of a dynamic RAM according to a fifth embodiment of the present invention. In the fifth embodiment, the partial decoding method is the same as in the third and fourth embodiments. However, if the decoder is CMO
The difference is that the circuit is constituted by an S circuit, a precharge signal is not input, and a noise killer circuit is not connected to the output wiring of the row decoder.

As shown in FIG. 19, a word line driving PMOSFET 23 connected to a word line WL and an NMO
The gates of the SFETs 24 are commonly connected, and are directly connected to the output wiring a of the VPP row decoder 50.
Of course, as described above, a VPP inverter for delay may be provided. This row decoder 50 is a CMOS-NAND controlled by address signals A2 to A4.
It consists of a gate. In the VPP supply circuit 51, a CMOS-controlled by the address signals A0 to A1 is provided.
It includes a partial decoder circuit portion composed of a NAND gate. Both decoder circuits are supplied with VPP as power. These address signals A0 to A4 control the PMOSFET. However, in order to completely turn off the PMOSFET when the address signal is at the H level, the address signal must be a VPP control signal. VCC by conversion circuit
The level is converted from the system control signal to the VPP system control signal. In this embodiment, since one level conversion circuit is used for one control signal, at least five level conversion circuits are required. However, in consideration of the driving capability of the level conversion circuit, one level conversion circuit is used. It is also possible to provide a plurality of level conversion circuits. In any case, the level conversion circuit requires a far smaller number than the conventional technology, so that the chip area and power consumption can be reduced, and a dynamic RAM which is less likely to malfunction can be provided. A similar effect is achieved. Further, in this embodiment, there is another effect that a high-speed operation becomes possible. That is, since the decoder circuit is not an NMOSFET but a CMOS circuit, it is not necessary to input a precharge signal in advance, charge an output terminal of the decoder, and then input an address signal. Can be planned. The output terminal of the decoder is VP
Since it is fixed at the P level or the VSS level and does not become floating, there is an effect that the potential level is hardly fluctuated even when the noise killer circuit is not connected to the output wiring a.

The storage device according to the fifth embodiment cannot apply the technique of level-converting only the precharge signal. However, in the storage device according to the fifth embodiment, the killer drive circuit is operated at VCC to reduce the consumption of VPP, and the word line noise killer circuit array 102 is provided between the word line drive circuit array and the memory cell array. The technology for achieving high integration density while suppressing noise interference can be applied.

In the first to fifth embodiments, the NAND gate is used as the row decoder.
An OR gate may be used. FIG. 20 is a circuit diagram of a word line selection circuit using a NOR gate 60 composed of an NMOSFET as a row decoder.

As shown in FIG. 20, the PMOSFET 61 included in the noise killer circuit is not directly connected to the output line a of the row decoder 61, and the VPP inverter 62
Connected indirectly via It should be noted that the connection in this specification is used in a sense that the connection relationship includes both direct and indirect.

[0104]

As described above, according to the present invention, it is possible to provide a semiconductor memory device that consumes less boosted potential.

[Brief description of the drawings]

FIG. 1 is a block diagram of a dynamic RAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a word line selection circuit shown in FIG. 1;

FIG. 3 is a circuit diagram of the level conversion circuit shown in FIG. 1;

FIG. 4 is a circuit diagram of the VPP generation circuit shown in FIG. 1;

FIG. 5 is a circuit diagram of a word line selection circuit according to a modification.

FIG. 6 is a block diagram of a dynamic RAM according to a second embodiment of the present invention.

FIG. 7 is a block diagram of a dynamic RAM according to a third embodiment of the present invention.

FIG. 8 is a block diagram of a dynamic RAM according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram of the word line selection circuit shown in FIG. 8;

FIG. 10 is a circuit diagram of the word line drive signal line selection circuit shown in FIG. 8;

FIG. 11 is a diagram showing a chip layout of the dynamic RAM shown in FIG. 8;

FIG. 12 is a plan view of the word line drive circuit array and the word line noise killer circuit shown in FIG. 11;

FIG. 13 is a plan view of the word line drive signal drive circuit array and the killer drive circuit array shown in FIG. 11;
(A) is a plan view of the word line drive signal drive circuit array 103-1 and the killer drive circuit array 104-1. (B) is a word line drive signal drive circuit array 103-2 and the killer drive circuit array 104-2. FIG.

FIG. 14 is a pattern plan view after forming a word line.

FIG. 15 is a plan view of the memory cell array shown in FIG. 11;

FIG. 16 is a sectional view of the memory cell shown in FIG. 15;

FIG. 17 is a sectional view of the word line drive circuit array, the word line noise killer circuit array, and the memory cell array shown in FIG. 11;

FIG. 18 is a diagram showing a chip layout of blocks of the dynamic RAM shown in FIG. 8;

FIG. 19 is a circuit diagram of a dynamic RAM according to a fifth embodiment of the present invention.

FIG. 20 is a circuit diagram of a word line selection circuit having a row decoder using a NOR gate.

FIG. 21 is a block diagram of a conventional word line selection circuit.

FIG. 22 is a block diagram of another conventional word line selection circuit.

[Explanation of symbols]

10 memory cell, 11 word line drive circuit, 12 V
PP supply circuit, 13 VPP-based row decoder, 14 V
PP generation circuit, 15 level conversion circuit, 16 word line selection circuit, 17 noise killer circuit, 18 inverter, 19 inverter, 21 transfer transistor, 22 capacitor, 23 P-channel MOSF
ET, 24: N-channel type MOSFET, 26: P-channel type MOSFET, 29: Decoding circuit unit, 30: Inverter, 39: Word line drive signal line selection circuit, 40:
Partial decoder, 41: Word line noise killer circuit, 43: Word line drive signal line drive circuit, 44: Noise killer circuit, 45: P-channel MOSFET, 46 ...
N-channel MOSFET, 47 ... killer drive circuit, 4
8 ... P-channel type MOSFET, 49 ... N-channel type M
OSFET, 100: memory cell array, 101: word line drive circuit array, 102: word line noise killer circuit array, 103: word line drive signal line drive circuit array, 104: killer drive circuit, 105: main row decoder array, 106 ... -Char decoder array, 10
7 ... level conversion circuit area, 108 ... capacitor area, 1
09: VPP generation circuit region, 200: buried plate trench cell, 201: capacitor, 202: N-type silicon layer (buried wiring layer), 203: trench.

Claims (8)

(57) [Claims] A low-potential power supply line to which a low potential is applied; a high-potential power supply line to which a high potential is applied; a booster circuit for generating a boosted potential higher than the high potential; A wiring, at least one word line to which a plurality of memory cells are connected, a main row decoder, a gate electrically connected to an output wiring of the main row decoder, a source connected to the boosted potential wiring, A word line driving circuit including a P-channel insulated gate FET having a drain connected to a word line; and a word line noise killer circuit having a drain connected to the word line and a source connected to the low potential power supply line. An input connected to at least one word line selection circuit, a partial decoder, and an output line of the partial decoder; Drive circuit that outputs a signal for driving the word line noise killer circuit to a first drive circuit that outputs a signal for driving the word line noise killer circuit, and a first drive circuit that outputs a signal for driving the word line noise killer circuit. At least one boosted potential wiring line selection circuit including a circuit, wherein the first drive circuit is operated with a potential difference between the boosted potential and the low potential, and the second drive circuit is connected to the high potential A semiconductor memory device operated by a potential difference from the low potential. 2. The main row decoder, one end of which is connected to an output wiring of the main row decoder, and a row decode circuit section controlled by an address signal, wherein the boosted potential is supplied to a source, and the main row decoder outputs A drain connected to the wiring, a P-channel insulated gate FET controlled by a precharge signal, wherein the partial decoder has one end connected to an output wiring of the partial decoder and is controlled by another address signal; A partial decode circuit section and a P-channel insulated gate FET that is supplied with the boosted potential to a source, has a drain connected to an output wiring of the partial decoder, and is controlled by another precharge signal. The semiconductor memory device according to claim 1. 3. The plurality of N-channel insulated gate FETs connected in series between an output wiring of the main row decoder and the low potential power supply line.
The partial decode circuit section includes a plurality of N-channel insulated gate FETs connected in series between an output wiring of the partial decoder and the low potential power supply line. 3. The semiconductor memory device according to claim 1. 4. The output wiring of the main row decoder,
P-channel insulated gate FET of the word line drive circuit
4. The semiconductor memory device according to claim 3, wherein an output wiring of the partial decoder is directly connected to a P-channel insulated gate FET of the first drive circuit. 5. The output line of the main row decoder,
P-channel insulated gate FET of the word line drive circuit
And the output wiring of the partial decoder is connected to the P-channel insulated gate FET of the first drive circuit via the even number of inverter circuits. 4. The semiconductor memory device according to claim 3, wherein: 6. A drain is connected to an output line of the main row decoder, and the boosted potential is supplied to a source.
A P-channel insulated gate FET having a gate connected to an output wiring of the main row decoder via an inverter circuit, a drain connected to an output wiring of the partial decoder, the boosted potential being supplied to a source, 5. The semiconductor memory device according to claim 4, further comprising: a P-channel insulated gate FET having a gate connected to an output wiring of the partial decoder via an inverter circuit. 7. A drain is connected to an input of a first-stage inverter circuit of the even-numbered inverter circuits connected to an output wiring of the main row decoder, the boosted potential is supplied to a source, and the first-stage inverter is provided. P-channel insulated gate type F with gate connected to the output of the circuit
ET and, among the even number of inverter circuits connected to the output wiring of the partial decoder, a drain is connected to an input of the first-stage inverter circuit, a source is connected to the boosted potential, and the first-stage inverter circuit is connected. 6. The semiconductor memory device according to claim 5, further comprising: a P-channel insulated gate FET having a gate connected to the output of said P-channel type. 8. A plurality of said word line selection circuits, said precharge signal is commonly input to said main row decoder included in each of said plurality of word line selection circuits, and a plurality of said boosted potential line selection circuits are provided. 8. The semiconductor according to claim 1, wherein said another precharge signal is commonly input to said partial decoder included in each of said plurality of boosted potential line selection circuits. Storage device.