WO1997047088A1

WO1997047088A1 - Semiconductor integrated circuit

Info

Publication number: WO1997047088A1
Application number: PCT/JP1996/001502
Authority: WO
Inventors: Mitsugu Kusunoki; Nobuo Tamba
Original assignee: Hitachi, Ltd.
Priority date: 1996-06-04
Filing date: 1996-06-04
Publication date: 1997-12-11

Abstract

A variable logic circuit composed of a plurality of memory cells, transfer gates arranged in a pyramid-like connection and serving as signal transmitting means for transmitting values stored in the memory cells to a common output node, and an output logical gate. Different signals instead of a common input signal are inputted to the control terminals of the first-stage transfer gates connected to the memory cells. The output signal from the output logical gate is fed back to one of the first-stage transfer gates. Consequently a flip-flop can be constructed by modifying the circuit a little. The structure of a logic block can be simplified and so the area occupied thereby is reduced. The number of logics can be increased.

Description

Specification

Semiconductor integrated circuit technology

The present invention relates to a semiconductor integrated circuit technology and a technology effective when applied to a variable logic integrated circuit whose logic function can be changed by data stored in a memory element. For example, a user can freely configure logic. Technology that is effective for use in simple programmable logic LSIs (large-scale integrated circuits). The above-described programmable logic LSI includes a field programmable gate array (FPGA), a field programmable logic array (FPLA), and the like.

Conventionally, for example, an FPGA as shown in FIG. 19 is known as a user-programmable logic LSI. The FPGA shown in Fig. 19 has a logic block PLB that allows the user to select any logic function, a crosspoint switch CPS placed between the left, right, top and bottom logic blocks, and a diagonal logic block. It consisted of a switch matrix SMX placed between the switches. In the logic block PBL, SRAM (Static Random Access Memory), ROM, fuse, etc. are arranged. By setting this information ("1" or "0", "conducting" or "non-conducting") from outside, the logic is set. The logic function of the block can be programmed.

The wiring between the logic blocks has a pattern formed in advance, and the presence / absence of connection between the wirings is set via the cross-point switch CPS and the switch matrix SMX. In the alpha point switch CPS and the switch matrix SMX, SRAM is arranged in the same way as a logic block. By setting this information ("1" or "0") from outside, the wiring pattern between logic blocks can be changed. Can be programmed. Such an FPGA is described, for example, in the journal “Information Processing” of Information Processing Society of Japan, Vol. 35, No. 6 PP 505-510, 1999. By the way, in the FPGA examined by the present inventors before the present invention, it is difficult to configure a flip-flop by a logic block or a large number of logic blocks are required. Therefore, as a logic block that composes a PFGA, for example, one that incorporates a flip-flop as shown in Fig. 1 has been proposed. The logic block shown in Fig. 1 is composed of a plurality of variable logic circuits LUTs that can configure any logic by storing in memory cells provided inside, and a selector SEL that selectively transmits the outputs of those variable logic circuits. And a flip-flop FF that latches and outputs a signal supplied from the selector.

Further, as shown in FIG. 2, for example, as shown in FIG. 2, the variable logic circuit LUT transmits eight memory cells MC 1 to MC 8 and the stored value of each memory cell to a common output node ηθ. M as a signal transmission means constructed in the shape of a pyramid (tree tree)

0 S (Metal Oxide Semiconductor) Transformer pair PT1 to PT4; Τ Τ5, ΡΤ6 and ΡΤ7 and output inverter connected to common output node ηθ

1 NV4, an inverter I NV1 which forms a signal for controlling the above-mentioned MOS transfer pair PT1 to PT4 based on the input signal INc, and a MOS transistor based on the input signal INb. An inverter I NV2 for forming a signal for controlling the lancet pair PT5 and PT6, and a signal for controlling the MOS transistor and a PT7 based on the input signal INa. Inverter I NV3.

However, the FPG A using the variable logic circuit shown in Fig. 2 requires a selector and a flip-flop, so the configuration is complicated and the occupation area of the logic block PLB is large, so that the degree of integration does not increase and the chip size increases. There is a problem that the yield increases as compared with a gate array of the same logical scale.

An object of the present invention is to provide a semiconductor integrated circuit capable of reducing the area occupied by a logic block and reducing the chip size.

Another object of the present invention is to provide a semiconductor integrated circuit having a logic block capable of forming a flip-flop circuit with a slight circuit change.

Another object of the present invention is to provide a semiconductor integrated circuit having a large number of achievable logics. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The outline of a typical invention disclosed in the present application is as follows.

That is, a plurality of memory cells, a transistor gate as a signal transmission means constructed in a viramid shape for transmitting the storage value of each memory cell to a common output node, and an output logic gate. In a variable logic circuit consisting of a gate and a gate, separate signals are input instead of inputting a common input signal to a control terminal of a first-stage transfer gate connected to each memory cell. As a result, the output signal from the output logic gate is fed back as a gate control signal to one of the first-stage transfer gates, thereby forming a flip-flop with only a slight circuit change. This makes it possible to simplify the configuration of the logic block, reduce the occupied area, and increase the number of achievable logics.

In the logic block shown in FIG. 1, a selector circuit is provided between the variable logic circuit and the flip-flop in order to effectively use a flip-flop having a relatively large number of elements. For example, since the variable logic circuit itself can be used as a flip-flop circuit, it is not necessary to provide a selector circuit and a flip-flop circuit separately from the variable logic circuit. Furthermore, the occupied area of the logic block can be reduced.

In addition, it is preferable to use a NAND gate as an output logic gate instead of an impeller. Thus, when a flip-flop is formed by feeding back the output signal from the output NAND gate to one of the above-described first-stage transfer gates as a gate control signal, the other terminal of the output NAND gate is used. Can be used as a flip-flop set terminal.

Furthermore, by inputting a reset signal to the control terminal of the transfer stage at the end of the transfer stage built on the bottom of the viramid, the flip-flop with a set-reset terminal can be used. It becomes possible to configure. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing an example of a variable logic block discussed before the present invention by the present inventors.

FIG. 2 is a circuit diagram showing an example of a variable logic circuit of a conventional variable logic block. FIG. 3 is a circuit configuration diagram showing one embodiment of the variable logic block of the present invention.

FIG. 4 is a circuit diagram showing a specific example of a memory cell constituting a variable logic block. FIG. 5 is a circuit diagram showing a second embodiment of the variable logic block of the present invention.

FIG. 6 is a configuration diagram showing a connection example of a signal line to a memory cell constituting a variable logic block.

FIG. 7 is a circuit diagram showing an example of a configuration when a D-type flip-flop is configured using only one variable logic block in FIG.

FIG. 8 is a circuit diagram illustrating an example of a master / slave type flip-flop using two variable logic blocks in FIG.

FIG. 9 is a schematic layout diagram showing an example of layout of circuit positions of the variable logic block. FIG. 10 is a schematic layout diagram showing a layout example of the element layout of the variable logic blocks.

FIG. 11 is a plan view showing an example of a detailed layout of the variable logic block. FIG. 12 is a circuit diagram showing an embodiment of a switch matrix constituting the programmable logic LSI.

FIG. 13 is a circuit diagram showing an example of a path switch constituting the switch matrix of FIG.

FIG. 14 is an explanatory diagram showing a connection example in a switch matrix when a D-type flip-flop is configured using the variable logic block of FIG.

FIG. 15 is a circuit configuration diagram showing another embodiment of the switch matrix constituting the programmable logic LSI.

FIG. 16 is an explanatory diagram showing an example of connection in the variable logic block of FIG. 5 and the switch matrix when a D-type flip-flop is configured using FIG.

FIG. 17 is a block diagram showing an example of the programmable logic SI according to the present invention. FIG. 18 is a circuit diagram showing an example of a circuit for writing data to a memory cell constituting the variable logic block and the switch matrix.

FIG. 19 is a block diagram showing an example of a conventional programmable logic LSI. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a circuit diagram showing a first embodiment of the variable logic block constituting the semiconductor integrated circuit according to the present invention. Note that the variable logic block in FIG. 5 is an example of a 6-input logic having eight memory cells.

In FIG. 3, MC 1 to MC 4 are memory cells, respectively.The variable logic block in FIG. 3 transmits the stored values of these memory cells to a common output node ηθ, Based on the constructed MOS O (Metal Oxide Semiconductor) transfer gate PT1 to PT3 as the signal transmission means, the output NAND gate NG connected to the common output node ηθ, and the input signal W Inverter I NV1 that forms a signal that controls the above-mentioned MOS transfer pair PT1 and an inverter that forms a signal that controls the above-mentioned MOS transfer pair PT2 based on the input signal X. It comprises an NV2 and an impulse INV3 which forms a signal for controlling the above-mentioned MOS transfer pair PT3 based on the input signal INa. The other terminal of the output NAND gate NG is provided to enable input of the set signal S when a flip-flop is configured. This pin is fixed at the high level when normal logic is configured instead of flip-flop. Thus, the output NAND gate NG functions as an inverter.

The MOS transistor pair PT1 to PT3 and the inverters I NV1 to I NV3 are composed of a MOSFET (MOS Field Effect Transistor) or a MISFET (Metal Insulator Semiconductor Field Effect Transistor). Each of the MOS transistor pairs PT1 to PT3 is composed of a pair of n-channel MOSFETs, and the inverters I NV1 to I NV3 are each composed of an n-channel MOSFET and a p-channel MOSFET.

Since the variable logic block of this embodiment is configured as described above, 25 logic functions can be realized according to the combination of the data ("1" or "0") stored in the recells MC1 to MC4 and the three input signals W, X, and INa. In the conventional variable logic circuit shown in FIG. 2, if the number of memory cells is four (the number of inputs is two), the number of logic functions that can be realized is 2 to the fourth power, that is, 16 ways. Logic circuits can implement more logic functions.

Table 1 shows formulas for the types of logic that can be realized by the variable logic circuit of this embodiment. In the formulas shown in the calculation formula column in Table 1, 2C1 indicates the number of combinations when lj is stored in one of the paired memory cells, and 2C2 indicates a pair. <2> indicates the number of combinations when `` 1 '' is stored in both of the memory cells. It indicates the number of valid signal combinations in consideration of the case where the same signal is input repeatedly (for example, when the inputs X and W are the same).

【table 1】

For example, as shown in FIG. 4, each of the memory cells MC1 to MC4 has a gate connected to a lead line WL and a drain connected to a data line DL. A latch circuit LT consisting of a pair of CMOS (Complementary M0S) impellers with input and output terminals combined, and an output connected to the other input / output node of this latch circuit LT It consists of an inverter INV0. When the memory cell of this embodiment is used, the desired data (“1” or “1”) is supplied by raising the above-mentioned line WL to a high level, turning on the MOSFET Qs, and supplying data from the data line DL. By writing "0"), the logic of the variable logic block can be uniquely set. The setting of this logic may be performed by an initialization process performed at the time of starting the system. If a static type memory cell such as SRAM is used as the memory cell, the logic set for each variable logic block can be changed for each initialization to provide the logic LSI with a different function. become able to.

The memory cells that make up the variable logic block are not limited to the static type as shown in Fig. 4, but the FMOS (Floating Gate Avalanche Injection MOSFET) that constitutes an EPROM (Erasable Programmable Read Only Memory), An electrically erasable programmable read only memory (EEPROM) such as a flash memory or a fuse element may be used.

FIG. 5 is a circuit diagram showing a second embodiment of the variable logic block constituting the semiconductor integrated circuit according to the present invention. Note that the variable logic block in FIG. 5 is an example of a 6-input logic having eight memory cells.

In FIG. 5, MC 1 to MC 8 are memory cells, respectively. The variable logic block in FIG. 5 transmits the stored values of these memory cells to a common output node ηθ, (Metal Oxide Semiconductor) transfer as a signal transmission means constructed in the shape of a pair PT1 to PT4; PT5, PT6 and

ΡΤ7, an output NAND gate NG connected to the common output node ηθ, and an inverter I NV1 that forms a signal for controlling the above-mentioned MOS transfer gate pair PTl based on the input signal W. An inverter I NV2 for forming a signal for controlling the MOS transfer transistor vs. PT2 based on the input signal X, and a MOS transfer target vs. PT3 based on the input signal Y. The inverter INV3 forms a signal for controlling the MOS transfer transistor pair PT4 based on the input signal Z, and the inverter INV4 forms a signal for controlling the PT4 based on the input signal Z. M S S transferer pair PT5, PT6, which forms a signal to control the PT6, and the MOS transfer transistor pair PT7 based on the input signal INa. And an inverter IVN6 for forming a signal for controlling the control signal.

Also in this embodiment, each of the MOS transistor pairs PT1 to PT7 is composed of a pair of η-channel MOS FETs, and the inverters I NV1 to IN V6 are n-channel MOSFETs, respectively. And a p-channel MOS FET. The other terminal of the output NAND gate NG is provided to enable input of the set signal ZS (valid low level) when a flip-flop is configured.

Since the variable logic block of this embodiment is configured as described above, data ("1" or "0") to be stored in each of the memory cells MC1 to MC8 and six input signals W, X, Y , Z, INa, INb, 1876 different logic functions can be realized. In the conventional variable logic circuit shown in Fig. 2, if the number of memory cells is eight (the number of inputs is three), the number of logic functions that can be realized is 2 to the eighth power, that is, 256. Circuits can perform much more logical functions.

Table 2 shows the formulas for the types of logic that can be realized by the variable logic circuit of this embodiment. 2C1 is the number of combinations when `` 1 '' is stored in one of the paired memory cells, and 2C2 is the pair The figure shows the number of combinations when “1” is stored in both memory cells. In addition, the last numbers “2”, “5”, and “15” in the formulas in the logical type F2 to F8 columns are used when the same signal is input as an input (for example, see Table 5). This indicates the number of valid signal combinations, as in the case where all four inputs are W, as in the case of signal type 1. Tables 3 to 5 show the specific signal combinations.

[Table 2]

[Table 3] Signal type Signal combination

1 WW

2 WX

[Table 4]

Signal type Signal combination

1 WWW

WWX

2 WX W xww

3 WX Y [Table 5]

In addition, the variable logic circuit of the present embodiment connects input signals X, INa, and INb by connecting common input signals (for example, X) to the first-stage transfer gates PT1 to PT4. It can operate as an 8 x 1-bit memory circuit that uses as an address signal.

FIG. 6 shows data writing to the memory cells when a static type memory cell as shown in FIG. 4 is used as the memory cells MC1 to MC8 constituting the variable logic block shown in FIG. An example of a more specific circuit configuration including a lead line and a data line for this purpose will be described. Although not particularly limited, the eight memory cells are arranged in two columns, and lead lines WL 1 and WL 2 are provided corresponding to each column, and are orthogonal to these lead lines. In this direction, four data lines DL1 to DL4 are arranged, and two memory cells MC are connected to each of the data lines DL1 to DL4. Hereinafter, two memory cells connected to the same data line are referred to as a pair.

As will be described later, a plurality of variable logic blocks PLB and a switch matrix SMX are arranged on an LSI chip in a checkered flag form, and each of the lead lines WL is placed in the lead line direction. The gate terminals of the MO SFET Qs for selecting the corresponding memory cell MC in the plurality of variable logic blocks PLB and the switch matrix S MX are connected to each other and the data lines DL To The drain terminals of multiple variable logic blocks PLB arranged in the data line direction and the corresponding MOS cells for selecting the corresponding memory cells in the switch matrix SMX are commonly connected. A specific example of the switch matrix SMX and the overall configuration of the variable logic LSI will be described later.

The end of each data line DL in FIG. 6 is not particularly limited. To prevent this, a pull-up MOS FET should be connected.

Fig. 7 shows an example of wiring when a D-type flip-flop is constructed using only one variable logic block of Fig. 5, and Fig. 8 uses two variable logic blocks of Fig. 5. Examples of the case where the master / slave type flip-flop is configured are shown.

As shown in FIG. 7, when the variable logic block of the embodiment of FIG. 5 is made to function as a flip-flop, the output signal of the output NAND gate NG is, for example, the second MOS gate. The transfer signal is fed back to the control terminal of the transfer gate PT2, the data signal D is input to the control terminal of PT1 as the input signal W, and the clock signal CK is input to the control terminal of PT5 as the input signal INb. However, the reset signal ZR is input to the control terminal of the PT 7 as the input signal INa. In addition, the control terminals of the MOS transistors PT3 and PT4 are fixed at the high level "L" or high level "H" so that the NG input signal at reset can output "1" stably. . As shown in FIG. 8, when a master-slave type flip-flop is configured by using two variable logic blocks of the embodiment of FIG. 5, one (previous stage) variable logic block B 1 is used. The output signal of the NAND gate NG is fed back to the control terminal of the first MOS transistor PT1, for example, and the control signal of PT2 is input to the control terminal of PT2 as the data signal D as the input signal X. However, the clock signal / C is input to the control terminal of PT5 as the input signal INb, and the reset signal / R is input to the control terminal of PT7 as the input signal INa.

Also, the output signal of the output NAND gate NG of the other (later stage) variable logic block B2 is fed back to, for example, the control terminal of the second MOS transfer gate PT2. The PT1 control terminal receives the output signal Q1 of the preceding logic block as the input signal X, the PT5 control terminal receives the clock signal C as the input signal INb, and the PT7 The reset signal / R is input to each control terminal as the input signal INa. In both logic blocks, the control terminals of the MOS transfer gates PT3 and PT4 are controlled so that the input signal of NG at reset will output `` 1 '' stably, and the output level will be `` L '' or It is fixed at level "H".

FIG. 9 shows an outline of an example of the layout of the variable logic block PLB in FIG. 5, FIG. 10 shows the layout of the MOS arrangement, and FIG. 11 shows the detailed layout (FIG. 10). (Layout with wiring added to Fig. 2). In FIG. 9, the regions surrounded by dotted lines are the memory cells MC1 to MC8, the MOS transistor pair PT1 to PT7, the output NAND gate NG, and the inverter I shown in FIG. The regions where NV1 to NV6 are respectively formed are shown. In Fig. 10, the hatched vertical elongated pattern is the polysilicon layer that is to be the gate electrode of the MOSFET, and the rectangular area separated by these polysilicon layers is the MOSFET. This is the diffusion layer that becomes the source and drain regions. The dotted line in FIG. 10 indicates the boundary of the element region in FIG.

The power supply lines are marked with VDD and VSS. For example, a power supply voltage of 3 to 5 V is applied to VDD, and a reference voltage of 0 V, which is lower than the power supply voltage, is applied to VSS, for example. As shown in Fig. 11, the variable logic block PLB consists of a first-layer metal wiring layer M1 without hatching and mesh and a second-layer metal layer with light mesh. The circuit is formed by the wiring layer M2. In this embodiment, among the six input signals, the terminals to which W, X, Υ, and Z are inputted are provided on each side of the variable logic block PLB, and the terminals to which the input signals INa and INb are inputted Are provided on the left and right sides of the block, respectively (further, the input terminal for the set signal ZS is provided on the lower side of the block.

On the other hand, the variable logic block PLB of this embodiment has an output terminal OUT on the upper side, and is configured to output a signal indicating a logical result from the output terminal OUT. The input / output terminals (W, X, Y , Z, IN a, IN b, OUT) can be routed through wirings M 1 and M2 via the third metal wiring layer M3 and the fourth metal wiring layer M4. Variable wiring Pro click PLB corresponding is connected to a control terminal of the element (gate electrode) _c Thus embodiments of the variable logic block PLB is 1 to logic桔果of the signal input from four directions Although the signal is transmitted in the direction, the direction in which the input signal enters and the direction in which the signal is output are not limited to those shown in FIG. For example, an output terminal may be provided on each of the upper, lower, left and right sides of the variable logic block PLB so that a signal indicating a logic result can be output in four directions.

In the layout of FIG. 11, the ground lines WL 1 and WL 2 and the lateral power lines VDD and VSS are formed by the first metal wiring layer M 1, and the data lines DL 1 to DL 1 The fourth and vertical power lines VDD and VSS are formed by the second metal wiring layer M2. Furthermore, the input / output terminals (W, X, Y, Z, I Na,

1Nb, OUT), the horizontal wiring with a high mesh is formed by the third metal wiring layer M3, and the vertical wiring with the thick hatching is applied. The wiring is formed by a fourth metal wiring layer M4.

Next, an embodiment of the switch matrix SMX will be described with reference to FIGS. FIG. 12 is a conceptual diagram showing a first embodiment of the switch matrix SMX. The switch matrix SMX of this embodiment has input / output lines US 1, US 2; RS 1, RS 2; SS 1, SS 2, one end of which is connected to the input / output terminal of an adjacent variable logic block PLB. LS 1 and LS 2 extend inward from each side of the block, two each, and a logical block separated by switch matrices along the vertical and horizontal directions in the figure. Indirect connection wirings U l, U 2; R 1, R 2; S 1, S 2; L 1, L 2 each extending inwardly for connection between the blocks. The above input / output wiring US 1, US 2; RS 1, RS

2; SS 1, SS 2; LS 1, LS 2 are variable logic block-switch matrices which connect the switch matrix S MX and the variable logic block PL B Configure the wiring for connection between boxes.

R 1, R 2; S 1, S 2; L 1, L 2 and the I / O wiring US 1, US 2; RS 1, RS 2; SS I, SS 2; At the intersection with LS 1, LS2, there is a one-way path switch PS 1 that can arbitrarily connect / disconnect these wirings, and input / output wirings U l, R l, S 1 , L1 intersection and U2 At the intersection of R 2, S 2, and L 2, there is provided a 6-way path switch PS 2 that can selectively connect between these wirings.

As shown by the dotted line in the circle, the above-mentioned path switch PS 1 is used for the block indirect wiring U 1, U 2; R 1, R 2; S 1, S 2; L 1, L 2 and the above-mentioned input / output. Wiring US1, US2; RS1, RS2; SS1, SS2; LS1, LS2 can be arbitrarily connected or disconnected. This connection is performed by selecting connection or non-connection by setting the information of the memory cell in the pass switch PS1 to "1" or "0" as described later. The path switch PS 2 is connected between any two lines of input / output wiring U 1, R 1 .S 1, L 1 and between any two lines U 2, R 2, S 2, L 2 (broken line) Can be selected.

Note that each wiring shown in FIG. 12 does not show an actual wiring shape, but is shown in an abstract manner for easy understanding of wirings provided with pass switches. FIG. 13 shows a specific example of the above-mentioned pass switches PS1 and PS2.

Among them, Fig. 13 (A) shows an example of the configuration of the path switch PS2 that can be connected in six directions and is provided at the intersection of the wiring for connecting the logical blocks. Six switch MOSFETs SW1 to SW6 connected between signal lines and six memory cells MC I1 to! 6 connected to their gates! It is composed of VIC16. Fig. 13 (B) shows a specific example of a path switch PS1 that can be connected in only one direction, and a switch M OSFET SW connected between two orthogonal signal lines. It consists of a memory cell MC connected to the gate. As is clear from correspondence with FIG. 12, the switch matrix SMX of this embodiment includes 44 switch MOSFETs SW1 to SW6, SW and 44 memory cells MC.

Each of the switches MOSWET SW1 to SW6, SW is composed of n channels M0SFET. The memory cells MC I 1 to C 16, MC have substantially the same configuration (see FIG. 13C) as the memory cell used in the variable logic block PLB (see FIG. 4). The only difference is that it does not have an output inverter INVO.

The switch matrix SMX of this embodiment is provided at each intersection of the connection wiring. When data is written to any of the memory cells MCI1 to MC16 in the pass switch PS1, the switch MOSFET corresponding to the memory cell to which the data has been written is turned on, so that each is enabled. It is configured to transmit signals in the specified direction (multiple directions are possible).

FIG. 14 shows a case where a flip-flop is configured as shown in FIG. 7 by using two switch matrices SMX having the configuration of FIG. 13 adjacent to the variable logic block PLB of the embodiment of FIG. The following shows an example of connection. As shown in Fig. 14, the output terminal OUT of the variable logic block PLB is connected to the input / output wiring SS1 of the upper switching matrix SMX1 adjacent to it, and is connected between the logic blocks by the path switch PS11. After switching to the connection wiring L1, the path switch PS21 is used to switch to the wiring S1 for the logical block indirect connection, and via the free-space wiring of the logic block PLB, the lower »connection switch After entering the logic block indirect wiring U1 of the RIX SMX2 and switching to the wiring R1 for connecting logical blocks by the path switch PS21, the I / O wiring is performed by the path switch PS12. Connect to US2 and connect back to input terminal X of logical block PLB.

In the above case, the path switches PS 11 and PS 21 in the switch matrix SMX 1 and the path switches PS 21 and PS 12 in the switch matrix SMX 2 are turned on. Write data ("1" or "0") to the memory cell to be used. Thus, the signal output from the variable logic block PLB2 can be fed back to the variable logic block PLB simply by passing through the two path switches to form a flip-flop.

Fig. 15 shows another specific example of the switch matrix SMX, and Fig. 16 shows an example of indirect wiring when the flip-flop shown in Fig. 7 is constructed using the switch matrix of Fig. 15. Show. The switch matrix shown in Fig. 15 includes the input / output wirings LS 1 and LS 2 of each side and the logical block indirect wiring L 1 in addition to the path switch of the switch matrix shown in Fig. 12. , L2 and SSI, between SS2 and SI, S2, between RS1, 1152 and 111, between R2, between US1, US2 and Ul, U2. PS 32, PS 33, PS34, PS 35, PS36, PS 37, PS 38 are provided to output signals from adjacent logic blocks. It is possible to return to the original logical block with only one pass switch. As a result, when the flip-flop shown in FIG. 7 is configured using the switch matrix shown in FIG. 15, as shown in FIG. 16, as shown in FIG. The configuration can be achieved by only passing through the path switch PS 34 and the path switch PS 38 in the switch matrix SMX2.

FIG. 17 shows an embodiment of a layout of a programmable logic LSI as a semiconductor integrated circuit according to the present invention using the variable logic circuit and the switch matrix of the above embodiment.

In FIG. 17, the symbol SUB indicates a single semiconductor substrate (chip) such as single-crystal silicon, the PLB indicates a variable logic block whose logic function can be changed from outside, and the SMX indicates from outside. The switch matrix as a variable wiring circuit that can change the wiring indirect hindrance. The variable logic block PLB and the switch matrix SMX are two-dimensional directions, that is, the X direction (horizontal direction) in the X and Y coordinates. And the Y direction (longitudinal direction) are arranged so as to be staggered, that is, to form a checker flag pattern as a whole.

Then, along the two sides (the left side and the upper side in the figure) of the array of the variable logic block PLB and the switch matrix SMX, the variable logic block PLB and the switch matrix SMX are placed in the variable logic block PLB and the switch matrix SMX. An X decoder circuit X—DEC and a Y decoder & write circuit Y—DEC & WDR for selecting and writing data to the provided memory cells (described later) are provided. Input / output buffer cells I OB are arranged along the edge. Most of the input / output buffer cells IOB handle input / output signals to / from a logic circuit composed of the above-described variable logic blocks and switch matrices. Decoder circuit X-DEC or Y decoder & write circuit Y-Used as a circuit that handles input signals to DEC & WDR.

In the variable logic LSI of this embodiment, a wiring area is provided above the variable logic block PLB and the switch matrix SMX by applying the multilayer wiring technology. X decoder circuit X—DEC and Y decoder & write circuit Y—DEC & WDR installed in variable logic block PLB and switch matrix SMX The signal lines (word lines and data lines) up to the memory cell (described later) are formed using the above-mentioned wiring area provided above the variable logic block and the switch matrix. Is done.

FIG. 18 shows an example of a circuit configuration of a system for writing data to the memory cell. Although not particularly limited, this data writing system is operated at the time of system initialization, etc., separately from the original operation of the logic LSI. The normal operation of such a logic LSI and the memory cell write operation are switched, for example, by a control signal WM supplied from outside the chip to a mode switching control terminal. When this control signal WM indicates the memory cell write mode, an externally input address signal ADR is taken into the address input buffer circuit AIB, and the X decoder circuit X—DEC and the Y decoder circuit Y—DEC Is supplied and decoded.

The X decode circuit X—DEC is extended from the X decoder circuit X—DEC toward the variable logic block and the array section PLB & SMX of the switch matrix according to the input X address signal. Set one of the multiple lead lines WL to the selected level. The Y decoder circuit Y—DEC decode output is supplied to the write circuit WDR, and the write circuit WDR extends from the Y decoder circuit Y—DEC to the above-mentioned variable logic block and the array section PLB & SMX of the switch matrix. For example, one of the plurality of data lines DL selected is selected and, at that time, according to data information ("1" or "0") input from the outside via the data input buffer circuit DIB. To set the selected data line DL to high level or low level.

Note that I OB is a buffer circuit for input / output signals to and from the original logic section, which is composed of a variable logic block and a switch matrix. The input / output buffer circuit I OB, the address buffer circuit A IB, and the data input buffer circuit D IB are constituted by an input / output buffer cell I OC shown in FIG.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor. For example, a variable logic block is shown in Figure 5. It is not limited to a circuit configuration, and any circuit form may be used as long as the logic is variable. Industrial applicability

In the above description, mainly the case where the invention made by the present inventor is applied to a programmable logic LSI which is the field of use as the background has been described. However, the present invention is not limited to this, and ordinary logic It can be used as a variable logic circuit that constitutes a part of the circuit in LSI.

Claims

The scope of the claims

1. In a semiconductor integrated circuit having a plurality of variable logic blocks and a variable wiring circuit for arbitrarily connecting the variable logic blocks, the variable logic block includes a plurality of memory cells and a plurality of memory cells. Signal transmission means having a first transistor group provided corresponding to the memory cell for transmitting or blocking the stored information of the memory cell according to an input signal; and for outputting the signal transmitted by the signal transmission means. And an output logic gate.

2. In the signal transmission means, a second transistor group consisting of half of the first transistor group is connected to the next stage of the first transistor group, and finally connected to a pair of transistors. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured to be configured as follows.

3. Equipped with an even number of the above memory cells and an even number of the first transistors. The first transistor is a pair of two, and the control terminal of one of the paired first transistors is an input terminal. The control terminal of the other transistor is configured so that a signal input from the input terminal is inverted and supplied to the control terminal of the other transistor via an inverter. 3. The semiconductor integrated circuit according to claim 1.

4. In a variable logic integrated circuit having a plurality of variable logic blocks and a variable wiring circuit for arbitrarily connecting these variable logic blocks, the variable logic block includes a plurality of memory cells and a plurality of memory cells. Signal transmitting means having a first transistor group for transmitting or blocking the stored information of the memory cell in accordance with the input signal provided in correspondence with the memory cell, and outputting the signal transmitted by the signal transmitting means And a flip-flop circuit is formed by feeding back the output signal of the output logic gate to the control terminal of the first transistor group. Semiconductor integrated circuit.

5. The output logic gate is constituted by a two-input logic gate, a transmission signal from the transmission means is input to one input terminal of the two-input logic gate, and the other input terminal is connected to the other input terminal. 5. The semiconductor integrated circuit according to claim 4, wherein a signal for setting said flip-flop circuit to a set state is input.

6. A signal for resetting the flip-flop circuit is input to a control terminal of a last-stage transistor of the signal transmission means. 6. The semiconductor integrated circuit according to paragraph 4 or 5.

7. The semiconductor according to claim 4, 5 or 6, wherein a clock signal is input to a control terminal of the second transistor of the transmission means. Integrated circuit.

8. In a semiconductor integrated circuit having a plurality of variable logic blocks and a variable distribution circuit for arbitrarily connecting these variable logic blocks,

The variable logic block includes a plurality of memory cells, and a signal transmission means having a first transistor group provided corresponding to each of the memory cells and transmitting or blocking information stored in the memory cells according to an input signal. And an output logic gate for outputting a signal transmitted by the signal transmission means.

The variable wiring circuit includes a memory cell, and selectively turns on switch means provided between arbitrary signal lines in accordance with data stored in the memory cell to enable transmission of a signal. A semiconductor integrated circuit comprising a path switch.

9. A data write circuit for writing data to the memory cells in the variable wiring circuit and the memory cells in the variable logic block is provided, and the operation of the data write circuit is enabled or disabled. 9. The semiconductor integrated circuit according to claim 8, further comprising: a control terminal capable of inputting the control signal of claim 8.