JPH06244683A - D latch circuit with reset function - Google Patents

Abstract

PURPOSE:To enlarge margin to noise such as crosstalk or the like and to make the circuit suitable for compressing a logic amplitude so as to accelerate circuit operations by making a series gate into three steps. CONSTITUTION:Concerning an ECL logic circuit 2, balanced differential circuits are serially connected over three steps between power sources, and four pairs of differential transistors are used. Namely, differential paired transistors Q9 and Q10, and differential paired transistors Q11 and Q12 are arranged in the first step, differential paired transistors Q13 and Q14 are arranged in the second step, and differential paired transistors Q15 and Q16 are arranged in the third step. Then, the respective emitters of the differential paired transistors Q13 and Q14 are connected to the collector of the transistor Q15. The collector of the transistor Q16 is connected to the collector of the transistor Q12, and the respective emitters of the differential paired transistors Q15 and Q16 are connected through a constant current source transistor Q17, which sets an output current corresponding to a voltage Vcs impressed to the base, and a resistor R5 to a power source VEE.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ECL (emitter coupled logic) type D latch with reset.

[0002]

2. Description of the Related Art An example of a conventional D latch circuit using an ECL circuit will be described with reference to FIG. In the figure, the D latch circuit is a level shift circuit 51 to which a clock signal G is supplied, a first differential transistor circuit 52 that performs a current switching operation by the clock signal G, and a second difference to which a data signal D is supplied. The active transistor circuit 53, the third differential transistor circuit 54, the third differential transistor circuit, a positive feedback circuit 55 that holds a logic level, an output circuit 56, and the like. These circuits are formed between ground potential and a negative constant voltage source V _{EE of} , for example, -5.2 volt and a negative constant voltage source V _TT of -2 volt.

The level shift circuit 51 comprises a transistor Q51, a diode Di and a resistor R51 which are connected in series with each other, and shifts the clock signal G supplied to the base of the transistor Q51 to the negative voltage side. The first differential transistor circuit 52 includes a differential transistor pair Q52 and Q53 to which the clock signal G and the reference voltage V _BB2 shifted to the respective bases are applied, and an emitter corresponding to the control voltage VCS applied to the base. The current source transistor Q54 supplies a current to the emitters of both transistors Q52 and Q53, and a resistor 52 connected to the emitter of the transistor Q54. Second differential transistor circuit 5
3 uses the transistor Q53 as a current source transistor,
It comprises a differential transistor pair Q55 and Q59 to which a data signal D and a reference voltage V _BB1 are applied respectively to their respective bases. The third differential transistor circuit 54 includes a differential transistor pair Q56 and Q57 having the transistor Q52 as a current source transistor. A transistor Q5 whose base receives a reset signal in parallel with the transistor Q57.
8 are connected. The positive feedback circuit 55 includes a transistor Q6.
0 and Q61 and resistors R53 to R59 form a positive feedback loop that holds the logic output together with the differential transistor pair Q56 and Q57. The output circuit 56 is composed of an emitter follower including a transistor Q62 and a resistor R60, and the emitter of the transistor Q62 is connected to the data output terminal Q.

Next, the operation of the circuit will be described. EC
In the L circuit, a transistor having a common emitter is used in the non-saturation region, but for convenience of description, the expressions "on" and "off" are used for the transistor. In the above configuration, when the "L" level representing the through period of the clock signal in which the data is taken in by the latch circuit is applied to the clock terminal G, the transistor Q52 is turned off and the transistor Q5
3 is turned on and the differential transistor circuit 53 is activated. In this state, when the "L" level of the data signal D is supplied to the input terminal D, the transistor Q55 is turned off, the transistor Q59 is turned on, and the collector of the transistor Q59 is set to the "L" level. Therefore, the base potentials of the transistors Q61 and 62 are at "L" level,
The transistor Q62 is turned off and the "L" level is output to the Q output terminal.

When the "H" level of the data signal D is supplied to the input terminal D, the transistor Q55 is turned on, the transistor Q59 is turned off, and the collector of the transistor Q59 becomes "H" level. Therefore, the base potentials of the transistors Q61 and 62 become "H" level,
The transistor Q62 is turned on, and the "H" level is output to the Q output terminal.

In this through mode, current source transistor Q52 is off and transistor Q58 connected to it does not operate. Therefore, even if the reset signal R is applied to the transistor Q58, the reset operation of the output Q is not performed. In this way, when the "L" level is supplied to the clock terminal G, the data signal D
"H" or "L" level of is output to the Q output terminal.

On the other hand, when the "H" level representing the hold period in which the latch circuit should hold the data is applied to the clock terminal G, the transistor Q52 is turned on, the transistor Q53 is turned off, and the differential transistor circuit 53 is turned on. Is deactivated and the differential transistor circuit 54 is activated.
When the clock signal G rises to the "H" level, the base of the transistor Q62 is set to the "L" level (logic output Q
L) is held, the transistor Q61 of the positive feedback circuit 55 is turned off, the base is biased to a substantially negative voltage V _EE by the resistor R54, the transistor Q56 is turned off, the transistor Q60 is turned on, and the transistor Q57 is turned on.
And a positive feedback loop is formed and the transistor Q57
The collector (base of the transistor Q62) potential is held at "L" level.

Similarly, when the clock signal G rises to the "H" level, if the "H" level (the logic output Q is H) is held at the base of the transistor Q62,
The transistor Q61 of the positive feedback circuit 55 is turned on, the base is forward biased, the transistor Q56 is turned on, the transistor Q60 is turned off, the transistor Q57 is turned off, and a positive feedback loop is formed to form the collector of the transistor Q57 (the base of the transistor Q62). ) The potential is held at the “H” level.

When the clock signal G is at "H" level and the differential transistor circuit 54 is activated by the transistor Q52, the reset signal R becomes the transistor Q.
When applied to the base of 58, transistor Q58 turns on. As a result, the base of the transistor Q62 is pulled to the "L" level, the transistor Q62 is turned off, and the "L" level in the reset state is output to the output terminal Q. In addition, the transistor Q61 of the positive feedback circuit
The base of is pulled to "L" level, and transistor Q5
6 off → transistor Q60 on → transistor Q57
The route of turning on the base of the transistor Q62 to "L" is held. As a result, the above ECL circuit functions as a D latch.

[0010]

However, in the conventional single-ended D-latch with reset, the noise margin has a reference voltage (eg, V _BB1 , V _BB2 ) and an input signal (eg, data signal D, clock signal). Since it is the difference from the “H” level or “L” level of G),
It is difficult to secure a noise margin in an ECL circuit that operates at high speed with a small signal amplitude.

Therefore, it is an object of the present invention to provide a D-latch with a reset function that can be used even in a device that requires a severe noise margin against crosstalk and the like.

[0012]

In order to achieve the above object, a D-latch circuit with a reset function according to the present invention is provided with a first differential transistor pair in which a first balanced signal is supplied to a differential input terminal. Second differential transistor pair whose dynamic output terminals are connected to the differential output terminals of the first differential transistor pair with the same polarity, and two bases are respectively connected to the differential output terminals of the second differential transistor pair. A pair of emitter follower transistors whose two emitters are respectively connected to the differential input terminals of the second differential transistor pair so as to be positively fed back, and the first and second emitter-follower transistors in response to a second balanced signal. A third differential transistor pair that supplies an emitter current to one of the differential transistor pairs, and an emitter of the third differential transistor pair and the second differential transistor in response to a third balanced signal. Characterized in that it comprises a fourth differential transistor pair to draw to a predetermined potential to either the collector.

[0013]

A pair of differential transistors of the third stage is further provided below the differential D latch of two stages of series gates, and the collector of one of the transistors is coupled to the emitter of the second stage of the differential D latch. And the collector of the other transistor is connected to the collector of one differential transistor pair of the differential D-latch. By using such a series gate three-stage configuration and driving the added differential transistor pair by the reset signal, the reset function of the D latch can be realized.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a D-latch circuit according to the embodiment, which is roughly classified into a level shift circuit 1 formed by transistors Q1 to Q8 and resistors R1 to R4, transistors Q9 to Q17, and resistors R5 to R8. ECL logic circuit 2, transistors Q18-Q1
9 and output circuit 3 formed by resistors R9 to R10
It is divided into three. The level shift circuit 1 and the ECL logic circuit 2 are formed between the ground potential and a negative constant voltage source V _EE of, for example, -5.2 volt. The output circuit 3 has a negative constant voltage source V of, for example, −2 V, which has a value lower than the ground potential and V _EE.
Formed during _TT .

The ECL logic circuit 2 is constructed by connecting balanced differential circuits in three stages in tandem between power supplies, and four differential transistor pairs are used. The first stage has a differential transistor pair Q9 and Q10 and a differential transistor pair Q11 and Q1.
2, the second stage has a differential transistor pair Q13 and Q14,
A differential transistor pair Q15 and Q16 is arranged in the third stage. The collector of the transistor Q9 has resistors R6 and R
It is connected to the ground potential via 7. Transistor Q12
Is connected to the ground potential via resistors R8 and R7. The collectors of the transistors Q9 and Q11 are connected to the base of the transistor Q18 of the output circuit 3.
The collectors of the transistors Q10 and Q12 are connected to the base of the transistor Q19 of the output circuit 3. The collectors of the transistors Q18 and Q19 are both connected to ground, and the emitters are connected to the power supply V _TT via resistors R9 and R10, respectively. The emitters of the transistors Q18 and Q19 are connected to the data output terminals QN and Q, respectively. Complementary logic outputs are obtained at the output terminals QN and Q. The emitters of the transistors Q18 and Q19 are connected to the bases of the differential transistor pair Q11 and Q12, respectively. The differential transistor pair Q11 and Q12 and the transistors Q18 and Q19 form a positive feedback loop holding two complementary logic outputs.

Each emitter of the differential transistor pair Q9 and Q10 is connected to the collector of the transistor Q13.
The emitters of the differential transistor pair Q11 and Q12 are connected to the collector of the transistor Q14. Each emitter of the differential transistor pair Q13 and Q14 is connected to the collector of the transistor Q15. The collector of the transistor Q16 is the collector of the transistor Q12 (hence,
It is connected to the collector of the transistor Q10 and the base of Q19). The emitters of the differential transistor pair Q15 and Q16 are connected to the power supply V _EE via a constant current source transistor Q17 and a resistor R5 that set the output current by the applied voltage V _cs to the base.

Data input terminals D and DN, to which a data signal which is a balanced output from the preceding stage (not shown) is supplied, are connected to the bases of the differential transistor pair Q9 and Q10, respectively.

A clock signal and a reset signal, which are balanced outputs from the previous stage, are supplied to the ECL logic circuit 2 via the level shift circuit 1. The level shift circuit 1 for biasing the supply signal corresponding to the ECL logic circuit 2 in which differential transistors are cascaded in three stages is composed of four series circuits. The first series circuit is composed of a transistor Q1, a resistor R1 and a diode Q2 which are connected in series to each other. The second series circuit is composed of a transistor Q3, a resistor R2 and a diode Q4 which are connected in series with each other. The third series circuit is a transistor Q connected in series with each other.
5, a diode Q6 and a resistor R3, and supplies a negative reset signal supplied to the reset terminal RN to the transistor Q5.
And the diode Q6 level-shifts by two stages and supplies it to the gate of the transistor Q15. The fourth series circuit is composed of a transistor Q7, a diode Q8 and a resistor R4 which are connected in series with each other, and outputs a positive reset signal supplied to the reset terminal R to the transistor Q7 and the diode Q.
The transistor Q16 is level-shifted by two steps by 8
Give to the gate.

In such a configuration, (1) When there is no reset command (transistor Q15 is on, transistor Q16 is off) and the state of the clock signal is in the through mode, the transistor Q13 is on and the transistor Q14 is off. When the transistor Q13 is turned on, the differential transistor pair Q9 and Q10 becomes active, and when the transistor Q14 is turned off, the differential transistor pair Q11 and Q12 becomes inactive and the positive feedback loop is cut off. Therefore, the logic level of the data signal is transferred to the output terminals QN and Q via the transistor pair Q9 and Q10 and the transistors Q18 and Q19.

(2) When there is no reset command (transistor Q15 is on, transistor Q16 is off) and the clock is in the hold mode, the transistor Q13 is off and the transistor Q14 is on. When the transistor Q13 is turned off, the differential transistor pair Q9 and Q10 becomes inactive, and when the transistor Q14 is turned on, the differential transistor pair Q11 and Q12 becomes active and a positive feedback loop is formed. Therefore, the fetching of the data signal is stopped, and the logic levels output to the output terminals QN and Q are held as they are by the transistors Q11, Q12, Q18 and Q19.

(3) When a reset command is issued (R;
H, RN; L), the transistor Q15 is turned off, and the transistor Q16 is turned on. When the transistor Q15 is turned off, the transistors Q13 and Q14 are both turned off, the data signal is not taken in, and the positive feedback loop is cut off. When the transistor Q16 is turned on, the base of the transistor Q19 is forcibly set to the low level, the transistor Q19 is turned off, and the output terminal Q is set to the "L" level regardless of the state of the clock signal.

(4) When the reset command is completed (R; L,
RN; H), and the above operations (1) and (2) are repeated from the state where the output terminal Q is at "L" level.

The operation of this circuit is a D latch which latches the data signal supplied at the falling edge of the clock signal G or the rising edge of the clock signal GN.

The D latch circuit described above can be configured not only by bipolar transistors but also by insulated gate type transistors and the like, and is not limited to the illustrated embodiment.

[0025]

As described above, the differential type D of the present invention is used.
Since the latch circuit has a configuration in which the series gate has three stages, it is possible to add the reset function to the D latch, and the addition of the reset function does not significantly increase the power consumption. Further, since the logic circuit portion of the latch is a fully differential circuit configuration, a logic signal input and output of a balanced signal can be obtained, a large margin for noise such as crosstalk, and a logic amplitude for speeding up the circuit operation. Suitable for compression of. Further, when the amplitude is the same as the conventional single type logical amplitude, there is more margin for noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 1 level shift circuit 1 2 ECL logic circuit 3 output circuit

Claims (1)

[Claims] 1. A first differential transistor pair to which a first balanced signal is supplied to a differential input terminal, and a differential output terminal connected to the differential output terminal of the first differential transistor pair with the same polarity. A second differential transistor pair, and two bases are respectively connected to the differential output terminals of the second differential transistor pair, and two emitters are positively fed back to the differential input terminals of the second differential transistor pair, respectively. A pair of emitter follower transistors that are connected to each other, and a third differential transistor pair that supplies an emitter current to either one of the first and second differential transistor pairs in response to a second balanced signal. A fourth differential transistor pair that pulls either one of the emitter of the third differential transistor pair and the collector of the second differential transistor to a predetermined potential in response to a third balanced signal, D latch circuit with a reset function, wherein the obtaining.