JP2693329B2 - Static flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a flip-flop circuit which performs a static operation in a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art As a conventional static type flip-flop circuit, there is known one using an ECL basic circuit as shown in, for example, the 1st conventional example shown in FIG.

In the figure, Q1 to Q18 are pilot transistors, R1 to R10 are resistors, GND is a ground terminal, and VE.
E is a power supply terminal, and VCS is a constant current source terminal. CK is a clock signal input terminal, CK with a bar (hereinafter referred to as “CK (bar)”) is a complementary clock signal input terminal,
Q is a true signal output terminal, Q with a bar (hereinafter "Q
(Represented by "(bar)") is a complementary signal output terminal.

In the flip-flop circuit according to the first conventional example, the master circuit 9 has two sets of upper differential pairs (transistors Q1 and Q which are differential pairs for reading data).
2, and a transistor Q that is a data holding positive feedback differential pair
3, Q4), one lower differential pair (transistor Q5,
Q6) is generally constituted by load resistors R1 and R2 common to the data reading differential pair and the data holding positive feedback differential pair, and the slave circuit 10 has the same circuit configuration as the master circuit 9. The output of the slave circuit 10 is connected so as to be fed back to the input of the master circuit 9. Here, since the present flip-flop circuit performs a digital operation, its maximum operating frequency is l / 2tpd.
(Tpd is limited by the propagation delay time of the master circuit and the slave circuit).

In this conventional example, the ground level is used to convert the signal levels of the transistors Q3 and Q4 of the master circuit 9 and to enhance the driving capability when driving the transistor transistors Q10 and Q11 of the slave circuit 10 of the next stage. And the power supply terminal VEE between the emitter follower circuit (transistor Q
8, resistor R6, transistor Q9, resistor R7) are connected.

As a second conventional example, the one shown in FIG. 8 is known (Japanese Patent Application No. 3-207048).
In the second conventional example, the lower differential pair is connected to the transistor Q2.
5, Q26 and transistors Q35, Q36 are different from the first conventional example, and the circuit operation can be speeded up as compared with the case of FIG.

In the circuit configuration of the second conventional example, a positive feedback differential pair for holding data (a differential pair consisting of transistors Q31 and Q32 for the master circuit 11 and a pair of transistors Q33 and Q34 for the slave circuit 12). The differential pair) has a lower operating current and a smaller transistor size than the first conventional example.
The mirror capacity of each differential pair can be reduced, the propagation delay time tpd can be shortened, and high-speed operation can be performed.

FIG. 2 is a signal waveform diagram showing the circuit operation of the above-mentioned first and second conventional examples.
As for the signal output from Q (bar), the clock signal is hi
Invert when changing from gh level to low level. Therefore, when the clock signal is input, a signal having a frequency obtained by dividing the clock frequency by 1/2 is output to the output terminals Q and Q (bar).

[0009]

However, according to the circuit configuration of the above-mentioned conventional example, a positive feedback differential pair for holding data (transistors Q31, Q32, and transistor Q3).
The operating current of the differential pair consisting of Q3 and Q34 is small because it is controlled by the load resistors R1 and R2 for data reading, and the gain of the differential pair is also small. As a result, the data holding time of the circuit is reduced. When it is long, in other words, when the circuit operates at low speed, there is a problem that the operation margin becomes small.

Further, in the circuit configuration of the above conventional example,
When the current consumption is reduced, there is a problem that the load resistance is increased in order to secure the logic amplitude and the operation speed is reduced.

The present invention has been made to solve the above-mentioned problems of the prior art, and a flip-flop circuit that secures a low-speed operation margin without losing high speed and enables low power consumption. It is intended to provide.

[0012]

In order to achieve the above-mentioned object, the present invention separates the load resistances of the data reading differential pair and the data holding differential pair so that the data reading differential pair and the data holding differential pair are separated. The circuit configuration is such that the gain of the differential pair for use can be set separately.

[0013]

The load resistance connected to the data reading differential pair and the load resistance connected to the data holding positive feedback differential pair are provided in a state of being separated from each other. The load resistance can be adjusted according to the operating current, and the gain of each differential pair can be controlled separately. Therefore, even if the operating current of the positive feedback differential pair for holding data is reduced in order to speed up the circuit operation, the output voltage of the differential pair for holding data can be sufficiently increased by increasing the load resistance. It is possible to increase the operational margin during low speed operation. In addition, because the load resistances of both differential pairs are separated, an emitter follower connected between the ground and the power supply terminal, which is used for signal level conversion and drive capacity enhancement when driving the next stage transistor, is used. The circuit can be omitted, and the power consumption can be reduced by the amount omitted.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment of the present invention. The flip-flop circuit according to this embodiment includes a master circuit 1 and a slave circuit 2. And
The master circuit 1 includes a pair of transistors Q41 and Q41.
The first upper stage circuit includes a first differential pair for reading data, which is constituted by 42, and a second differential pair for holding data, which is constituted by a pair of transistors QL1 and QL2. The pair of transistors Q41 and Q42 that form the first differential pair include a transistor QF that forms an emitter follower circuit at each collector.
1, a resistor R21, a transistor QF2, and a resistor R22 are connected to each other. Load collectors RL1 and RL2 are connected to collectors of the transistors QL1 and QL2, respectively, which form the second differential pair. In addition, in this embodiment and each of the following embodiments, the transistor is of a bipolar type.

The slave circuit 2 has the same structure as the slave circuit 1, and includes a third differential pair for reading data, which is composed of a pair of transistors Q43 and Q44, and a pair of transistors QL3. It has a second upper stage circuit composed of a fourth differential pair for holding data constituted by QL4. In the pair of transistors Q43 and Q44 forming the third differential pair, each collector has a transistor QF3 and a resistor R23 of an emitter follower circuit, a transistor QF4 and a resistor R24.
Are connected to each other, and the load resistance R is provided to the collectors of the transistors QL3 and QL4 forming the fourth differential pair.
L3 and RL4 are connected.

On the other hand, the true signal input terminal CK of the clock signal
Is connected to the bases of the transistors Q45 and QL6, and is a complementary signal input terminal CK (bar) of the clock signal.
The bases of the transistors Q46 and QL5 are connected to. The emitters of the transistors Q45 and Q46 are commonly connected, and the transistors QL5 and QL6 are connected.
Have their emitters connected in common.

The collector of the transistor Q45 is connected to the common emitters of the transistors Q41 and Q42 of the first differential pair, and the collector of the transistor QL5 is connected to the transistors of the second differential pair QL1 and QL2.
Connected to the common emitter of. Similarly, the collector of the transistor Q46 is connected to the common emitter of the transistors Q43 and Q44 of the third differential pair, and the collector of the transistor QL6 is connected to the common emitter of the transistors QL3 and QL4 of the second differential pair. It is connected.

Here, the pair of transistors Q45,
Q46 constitutes a first lower stage differential pair, and the pair of transistors QL5 and QL6 constitutes a second lower stage differential pair.

The collector of the transistor Q41 of the first differential pair is connected to the base of the transistor QL1 of the second differential pair and the base of the transistor Q43 of the third differential pair, and the first differential pair is connected. The collector of the transistor Q42 is connected to the base of the transistor QL2 of the second differential pair and the base of the transistor Q44 of the third differential pair.

The second differential pair of transistors QL1,
The collectors of QL2 are connected to the base of the transistor QF2 and the base of the transistor QF1, respectively, and the collectors of the transistors QL3 and QL4 of the fourth differential pair are connected to the base of the transistor QF4 and the base of the transistor QF3, respectively. .

Output terminals Q and Q (bars) are connected to the respective collectors of the transistors Q43 and Q44 of the slave circuit 2 and output to the bases of the transistors Q41 and Q42 of the master circuit 1, respectively. Terminal Q, Q
(Bar) is connected.

On the other hand, the common emitters of the differential pair transistors Q45 and Q46 of the first lower stage circuit are connected to the collector of the constant current source transistor Q47, and the differential pair transistor QL5 of the second lower stage circuit, The common emitter of QL6 is connected to the collector of the constant current source transistor QL7.

The bases of the transistors Q47 and QL7 are connected to the constant current source terminal VCS, the resistors R25 and R26 connected to the respective emitters are connected to the power supply terminal VEE, and the transistors QF1 to QF4 are connected. The collector and load resistors RL1 to RL4 are ground terminals G
Connected to ND.

Next, the circuit operation of the first embodiment constructed as described above will be described.

Before explaining the operation of this circuit, in the circuit of FIG. 1, when the clock signal is at low level, the output terminals Q and Q (bar) are respectively at high level (hereinafter referred to as H signal) and low level. The start state is when the signal (hereinafter referred to as the L signal) is output.

In the initial state, first, when the clock signal changes from the low level to the high level, the transistor Q45 is turned on, and the first differential pair for reading data of the master circuit 1 is activated.
The L signal and the H signal are input from the output terminals Q (bar) and Q to the bases of the transistors Q41 and Q42, respectively, and the H signal, which is an inverted signal of the input signal to each base, is input to the collectors of the transistors Q41 and Q42. The L signal is output respectively.

On the other hand, the slave circuit 2 in the initial state
Then, since the transistor QL6 is turned on and the fourth differential pair for holding data is turned on, the H signal and the L signal are input to the bases of the transistor transistors QL3 and QL4, and the transistors QL3 and QL4 are turned on. The L signal and the H signal, which are the inverted signals of the input signal to each base, are output to the collector, respectively.

The L signal or the H signal propagates through the transistor QF4 and the resistor R24, which are emitter follower circuits, or the transistor QF3 and the resistor R23, respectively, and the H signal and the L signal are output to the output terminals Q and Q (bar). Positive feedback is given,
The output terminals Q and Q (bar) respectively hold the states when the clock signal in the initial state is at the low level.

Next, when the clock signal changes from the high level to the low level, the master circuit 1
Since the second differential pair for holding data is in the operating state, the H signal and the L signal output to the collectors of the transistors Q41 and Q42 are input to the bases of the transistors QL1 and QL2, respectively, and the transistor QL1 is input. , QL2 outputs L signal and H signal which are inversion signals of the input signal to the base, respectively.

The L signal or the H signal propagates through the emitter follower circuit, a transistor QF2, a resistor R22, or a transistor QF1 and a resistor R21, respectively, and an H signal is output to the collectors of the transistors Q41 and Q42 which are the outputs of the master circuit 1. L signal is positively fed back and clock signal is high
Holds the state at the time of level.

On the other hand, in the slave circuit 2, the third differential pair for reading data is in operation and the transistor Q4
H and L signals are input to the bases of 3 and Q44, and output terminals Q and Q (bar) (in other words, transistor Q4
3, L and H signals, which are the inverted signals of the input signal to the base, are output to the collectors of Q3 and Q44, respectively.

As described above, the output states of the output terminals Q and Q (bar) are such that the clock signal changes from the high level to the low level.
Invert when changing to a level.

By repeating the above circuit operation, a signal having a frequency divided by half the input clock frequency as shown in FIG. 2 is output to the output terminals Q and Q (bar).

In this circuit configuration, the current path and load of the differential pair for reading data (first or third differential pair) and the differential pair for holding data (second or fourth differential pair). The resistance is independent.

As a result, the operating current and the size of the transistor of the data holding differential pair can be further reduced as compared with the conventional example, the time required for holding the data can be shortened, and the circuit speed can be increased. Further, it is possible to increase only the load resistances RL1 and RL2 of the data holding differential pair, and it is possible to increase the operation margin during low speed operation.

Furthermore, since the emitter follower circuit connected between the ground and the power supply terminal, which is required in the conventional circuit, is omitted, the power consumption can be reduced accordingly.

FIG. 3 shows a second embodiment of the present invention. In this embodiment, a second differential pair transistor QLll and QLl2 for holding data has a common emitter as a common emitter and a constant current source composed of a resistor R36, and a fourth differential pair transistor QLl3. In this configuration, a common emitter of QL14 is connected to a current source including a transistor QL6 and a resistor R37. In the case of this circuit configuration, the data holding differential pair (second and fourth differential pairs) is always in the operating state, but the circuit operation is the same as that of the first embodiment.

FIG. 4 shows a flip-flop circuit according to the third embodiment of the present invention. In this embodiment, the collector of the transistor Q65 is connected to the common emitter of the first differential pair (transistors Q61 and Q62) for reading data in the master circuit 5, and the second differential pair (transistors QL21 and QL22) for retaining data is used. The collector of the transistor Q66 is connected to the common emitter of the transistor Q66, and the collector of the transistor Q67 is connected to the common emitter of the third differential pair (transistors Q63 and Q64) for reading data in the slave circuit 6, and the fourth collector for holding the data is connected. In this configuration, the collector of the transistor Q68 is connected to the differential pair (common emitter of the transistors QL23 and QL24).

That is, the transistor transistors Q65 and Q6
6, and Q67 and Q68 form the first and second lower circuits. The circuit operation of this embodiment is similar to that of the first embodiment.

In the case of the present embodiment, a data reading differential pair (first differential pair or third differential pair) and a data holding differential pair (second differential pair or fourth differential pair). The operating currents of the pair) are equal and the operating current of the data holding differential pair cannot be reduced. However, since the size of the transistor of QL21 to QL24 can be reduced, the circuit operation can be speeded up.

FIG. 5 shows a fourth embodiment of the present invention. This embodiment is different from the first embodiment in that the data holding second differential pair transistors QL31 and QL32 are provided.
Transistor QL38 and resistor R5 on the common emitter of
A constant current source composed of 7 and a common emitter of the transistors QL33 and QL34 of the fourth differential pair.
The configuration is such that a constant current source composed of L39 and a resistor R58 is additionally connected. The circuit operation of the present embodiment is also the first
This is the same as the embodiment.

In the case of this embodiment, as compared with the first embodiment, the data holding differential pair does not become completely inoperative, so that the operating margin can be further increased during low speed operation. There is.

In the above-mentioned embodiments, the example using the bipolar transistor as the transistor has been described, but this circuit configuration can be realized by using the FET. Also, although an example of a T-type flip-flop circuit capable of frequency division operation as the flip-flop circuit has been described, the present circuit configuration also applies to the D-type flip-flop circuit in which the output of the slave circuit is not fed back to the input of the master circuit. Of course, it is applicable.

FIG. 6 shows the operating frequency range and power consumption of the flip-flop circuit according to the conventional example and the flip-flop circuit according to the first embodiment, the operating current of the data reading differential pair, and the data holding. 6 shows a simulation result of the relationship with the ratio of the operating current of the differential pair. As shown in the figure, it can be understood that the flip-flop circuit according to the present invention is stable in low-speed operation even if the operating current of the data holding differential pair is set small. Further, the power consumption of the circuit according to the present invention is reduced to about 1/3 to 1/5 of that of the circuit of the conventional example, and it can be understood that the intended purpose of low power consumption can be achieved. .

[0045]

In the static flip-flop circuit according to the present invention, the load resistance of the differential pair for reading data and the load resistance of the differential pair for holding data are separated so that the gain of each differential pair is increased. Can be set separately, and an operating margin can be secured during low-speed operation without impairing high-speed circuit operation, while low power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the circuit operation of the flip-flop according to this embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between an operating frequency range and power consumption, and a ratio of both operating currents of a data reading differential pair and a data holding differential pair.

FIG. 7 is a circuit diagram showing a first example of a conventional static flip-flop circuit.

FIG. 8 is a circuit diagram showing a second example of a conventional static flip-flop circuit.

[Explanation of symbols]

1, 3, 5, 7 master circuit, 2, 4, 6, 8 slave circuit, Q41, Q42 transistor (first differential pair), QL1, QL2 transistor (second differential pair), Q43, Q44 transistor (Third differential pair), QL3, QL4 transistors (fourth differential pair), RL1, RL2, RL3, RL4 load resistors, Q45, QL5, Q46, QL6 transistors (lower circuit).

Claims (3)

(57) [Claims] 1. A master circuit and a slave circuit are provided,
The master circuit has a first upper stage circuit including a first differential pair for reading data, which is composed of a pair of transistors, and a second differential pair for holding data, which is composed of a pair of transistors. However, the slave circuit is
It has a second upper stage circuit composed of a third differential pair for reading data composed of a pair of transistors and a fourth differential pair for holding data composed of a pair of transistors, while having a clock A first and a second lower stage circuit for inputting first and second signal states of a signal, and when the clock signal shifts from the first signal state to the second signal state, the first The second pair is activated when the differential pair and the fourth differential pair are operated to maintain the previous first output state and the clock signal transitions from the second signal state to the first signal state. Static type flip-flop circuit for operating the differential pair and the third differential pair to obtain the second output state, the pair of transistors forming the first to fourth differential pairs. to the collector, respectively, of each different load Static flip-flop circuit, wherein the anti has been connected. 2. The second master circuit according to claim 1,
Of the pair of transistors forming the differential pair of the above-mentioned differential pair and the fourth differential pair of the slave circuit are connected in common, and each of the commonly connected emitters is connected to a current source transistor. A static flip-flop circuit characterized by being connected to each other. 3. The first lower circuit according to claim 1, wherein
The second lower-stage circuit is composed of a pair of C and D transistors whose emitters are commonly connected, and the second lower circuit is composed of a pair of C and D transistors whose emitters are commonly connected. The collector of the transistor is connected to the commonly connected emitter of the pair of transistors forming the first differential pair, and the collector of the B transistor is connected to the common of the pair of transistors forming the third differential pair. And a collector of the C transistor is connected to a commonly connected emitter of a pair of transistors forming a second differential pair, and a collector of the D transistor is connected to a fourth differential pair. A static flip-flop circuit, characterized in that the static flip-flop circuit is connected to the commonly connected emitters of a pair of transistors constituting the.