JP2747467B2 - Static flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a static flip-flop circuit which operates statically in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 4 shows an ECL (Emitter Coupled Logi).
c) A configuration example of a conventional static flip-flop circuit using a basic circuit.

In FIG. 1, a master circuit 1 includes a resistor R
1, a data reading circuit comprising R1, R2 and transistors Q1, Q2, Q5, a data holding positive feedback circuit comprising resistors R1, R2, transistors Q3, Q4, Q6, transistors Q8, Q9 and resistors R6, R7; The current source circuit includes a transistor Q7 connected to a common emitter of the transistors Q5 and Q6 and a resistor R5. The slave circuit 2 includes a data reading circuit including resistors R3 and R4 and transistors Q10, Q11 and Q14, a resistor R3 and R4, and a transistor Q1.
2, a positive feedback circuit for holding data comprising Q13, Q15, transistors Q17, Q18 and resistors R9, R10, and a current source circuit comprising a transistor Q16 and a resistor R8 connected to a common emitter of transistors Q14, Q15. Is done. GND is a ground terminal, VE
E is a power supply terminal, and VCS is a constant current source terminal.

The transistors Q1 to Q7 and the resistors R1, R2 and R5, and the transistors Q10 to Q16 and the resistors R3, R4 and R8 each constitute a vertical stacked gate composed of a two-stage differential pair. Transistor Q
8, Q9, resistors R6, R7 and transistor Q1
7, Q18 and resistors R9, R10 each constitute an emitter follower circuit.

Here, the clock signal CK is input to the bases of the transistors Q5 and Q15, and the clock complement signal CK is input.
There is input to the base of the transistor Q6, Q14, the output terminal Q of the master circuit 1 ', Q' (base of transistor Q10, Q11) input terminal of the slave circuit 2 is connected, an output terminal Q of the slave circuit 2, Q The input terminal of the master circuit 1 (bases of the transistors Q1 and Q2) is connected in a feedback manner to form a static flip-flop circuit. Incidentally, Q, Q 'is an output terminal of the true signal, Q,
Q 'is an output terminal of the complementary signal.

In the static flip-flop circuit having such a configuration, when the clock signal CK goes high, the transistors Q5 and Q15 are turned on, and the transistors Q1 and Q2 and the transistors Q12 and Q13 are turned on.
A current path is formed in the differential pair consisting of Master circuit 1
The output signal of the slave circuit 2 which has been fed back to is inverted by the differential pair composed of the transistors Q1 and Q2, level-shifted through the transistors Q8 and Q9, and taken out to the output terminals Q 'and Q ' of the master circuit 1. . At this time,
Transistors Q6 and Q14 are supplied with low level clock complement signal CK and are in a non-conductive state.
No current flows through the differential pair composed of transistors Q3, Q4 and transistors Q10, Q11. Therefore, the signals taken out at the output terminals Q 'and Q ' of the master circuit 1 are not propagated to the slave circuit 2 but are held there.

Next, when the clock signal CK goes low and the clock complement signal CK goes high, the transistors Q6 and Q14 are turned on and the transistor Q6 is turned on.
3 and Q4 and transistors Q10 and Q11, a current path is formed, so that the signals taken out at output terminals Q 'and Q ' of master circuit 1
3, Q4 and transistors Q10, Q11. Since a positive feedback is applied to the differential pair including the transistors Q3 and Q4 by the emitter follower circuit, the output signal of the master circuit 1 is held while the clock signal CK is at the low level. On the other hand, the output signal of master circuit 1 propagated to slave circuit 2 is inverted by a differential pair including transistors Q10 and Q11, and transistors Q17 and Q17 are output.
The signal is level-shifted via 18 and taken out to the output terminals Q and Q of the slave circuit 2. At this time, the transistor Q
5 and Q15 are supplied with the low-level clock signal CK and are in a non-conductive state, and no current flows through the differential pair including the transistors Q1 and Q2 and the transistors Q12 and Q13. Therefore, the output terminals Q, Q
Are not propagated to the master circuit 1 and are retained there.

As described above, the signals taken out from the output terminals Q and Q of the slave circuit 2 repeat the inversion operation when the clock signal CK changes from the high level to the low level. Therefore, as shown in FIG. 5, a signal having a frequency half the frequency of the clock signal CK is output to the output terminals Q and Q of the static flip-flop circuit shown in FIG.

[0009]

In the configuration of the static flip-flop circuit shown in FIG. 4, the delay time of the master circuit 1 is the time T1 from the input of the clock signal CK to the output of the data signal to the emitter follower circuit.
And a differential pair having positive feedback (transistors Q3 and Q4)
And a time T2 until the input differential pair (transistors Q10, Q11) of the slave circuit 2 at the next stage is driven. Therefore, the master circuit 1 and the slave circuit 2
Are cascaded, the delay time is twice as long, and the maximum operating frequency is the reciprocal of this delay time. That is, the shorter the delay time, the faster the static flip-flop circuit operates.

The delay time T2 is determined by the differential pair having positive feedback (transistors Q3 and Q4) and the input differential pair of the slave circuit 2 at the next stage (transistors Q10 and Q1).
It is greatly affected by the mirror capacity of 1). However, in the conventional circuit configuration, it is extremely difficult to reduce the Miller capacitance, which has been a great obstacle to increasing the operation speed of the static flip-flop circuit.

According to the present invention, a differential pair having positive feedback (transistor Q3,
It is an object of the present invention to provide a static flip-flop circuit capable of increasing the speed by reducing the mirror capacitance of Q4).

[0012]

According to the first aspect of the present invention, there are provided two latch circuits, a master circuit and a slave circuit, each having a differential pair for reading data and a differential pair for holding data. In a static flip-flop circuit, a collector is connected to a common emitter of an upper differential pair for reading data of the master circuit, and an emitter of a first transistor to which a clock signal is input to a base, and a data of the slave circuit. The collector is connected to the common emitter of the upper differential pair for reading,
A base is connected to an emitter of a second transistor to which a clock complement signal is inputted, a first lower differential pair is formed for each upper differential pair, and a first current source circuit is connected to the common emitter. An emitter of a third transistor having a collector connected to a common emitter of the upper differential pair for holding data of the master circuit and a clock complement signal being input to a base, and an upper differential for holding data of the slave circuit; The collector is connected to the common emitter of the pair, the base is connected to the emitter of the fourth transistor to which the clock signal is input, and the second lower differential pair for each upper differential pair is formed to the common emitter. It is characterized in that a second current source circuit is connected.

According to a second aspect of the present invention, there is provided a static flip-flop circuit comprising two latch circuits of a master circuit and a slave circuit each provided with a differential pair for reading data and a differential pair for holding data. , A collector is connected to a common emitter of an upper differential pair for reading data of the master circuit, and an emitter of a first transistor whose base is supplied with a clock signal; and an upper differential for reading data of the slave circuit. The collector is connected to the common emitter of the pair, the base is connected to the emitter of the second transistor to which the clock complement signal is input, and the lower differential pair is formed for each upper differential pair, and the first emitter is connected to the common emitter. A second current source circuit is connected to the common emitter of the differential pair for data retention of the master circuit, Serial characterized by connecting a third current source circuit to the common emitter of the differential pair of data retention of the slave circuit.

[0014]

The Miller capacitance Cm of a differential pair having positive feedback is represented by the collector capacitance Cc of a transistor forming the differential pair.
Assuming that the voltage amplification factor of the differential pair is Ao, Cm = Cc (1 + Ao). Here, by reducing the operating current of the transistors forming the differential pair having positive feedback, the voltage amplification factor Ao can be reduced, and the mirror capacitance Cm of the differential pair having positive feedback can be reduced. It becomes possible.

According to the present invention, a differential pair having positive feedback (a differential pair for holding data) is combined with a differential pair for reading data and a differential pair for holding data in the master circuit and the slave circuit, respectively. The circuit design allows the operating current of (pair) to be reduced independently. Therefore, the delay time of the differential pair having positive feedback in the delay time T2 can be reduced, and the speed of the static flip-flop circuit can be increased.

Further, by forming a differential pair having a positive feedback by using a transistor having a small transistor size, the collector capacitance Cc can be reduced, and similarly, the Miller capacitance Cm can be reduced. It is possible to increase the speed of the circuit.

[0017]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention. In the figure, a master circuit 3 includes a resistor R1
1, R12 and transistors Q21, Q22, Q25
Data reading circuit comprising resistors R11 and R1
2. It has a data holding positive feedback circuit composed of transistors QL1, QL2, QL5, transistors Q28, Q29 and resistors R16, R17. Slave circuit 4
Are resistors R13, R14 and transistor Q23,
A data reading circuit including Q24 and Q26, resistors R13 and R14, and transistors QL3, QL4, and QL.
6, transistors Q30 and Q31 and resistor R19,
And a data holding positive feedback circuit comprising R20.

Here, in the conventional circuit shown in FIG. 4, transistors Q25 and QL5 or transistors Q26 and QL
6 constitute a lower differential pair, however, in the circuit according to the embodiment of the present invention, the transistor Q2 of the master circuit 3
5 and the transistor Q26 of the slave circuit 4 constitute a differential pair, the transistor QL5 of the master circuit 3 and the transistor QL6 of the slave circuit 4 constitute a differential pair, and a current source circuit is provided at the common emitter of each differential pair. The transistor Q27 and the resistor R15 and the transistor QL7 and the resistor R18 are connected. Note that GND is a ground terminal, VEE is a power supply terminal, and VCS is a constant current source terminal.

As described above, by adopting a circuit configuration for separating the data reading circuit including the current source circuit from the data holding positive feedback circuit, the current flowing through the data holding positive feedback circuit is reduced by the current flowing through the data reading circuit. It becomes possible to design smaller than. If the current flowing through the data holding positive feedback circuit can be reduced, the voltage gain Ao of the differential pair having positive feedback can be reduced,
The mirror capacitance Cm can be reduced. As a result, of the delay time T2, the delay time until driving the differential pair having positive feedback is reduced, and the static flip-flop circuit can be operated at high speed accordingly. In order to reduce the current flowing through the data holding positive feedback circuit, for example, a resistor R
18 is increased.

Further, by reducing the transistor size of the transistors QL1 to QL4 constituting the data holding positive feedback circuit, the collector capacitance and the substrate capacitance can be reduced, and similarly, the mirror capacitance Cm can be reduced. This allows the static flip-flop circuit to operate at high speed.

In the configuration of this embodiment, the connection relationship between the clock signal CK and the transistor to which the clock complement signal CK is input is the same as that of the conventional circuit, so that the operation is exactly the same as that of the above-described conventional circuit.

Here, regarding the circuit of the first embodiment, SP
FIG. 2 shows the relationship between the maximum operating frequency obtained by the ICE simulation and the operating current of the differential pair having positive feedback. In the figure, the horizontal axis represents the operating current (m) of the positive feedback differential pair.
A), and the vertical axis indicates the maximum operating frequency (GHz) of the static flip-flop circuit. As shown in the figure,
It can be seen that a significant increase in speed can be achieved by reducing the operating current of the differential pair having positive feedback.

FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention. In the figure, a master circuit 5 includes a resistor R
21, R22 and transistors Q41, Q42, Q4
5, a data reading circuit, and resistors R21 and R2.
2, transistors QL11, QL12, transistor Q
48, Q49 and a data holding positive feedback circuit composed of resistors R27 and R28. The slave circuit 5 includes resistors R23 and R24 and transistors Q43 and Q4.
4, a data reading circuit consisting of Q46 and a resistor R2
3 and R24, transistors QL13 and QL14, transistors Q50 and Q51, and a data holding positive feedback circuit including resistors R30 and R31.

Here, in the circuit of this embodiment, a transistor Q47 and a resistor R25, which form a current source circuit, are connected to a common emitter of the transistor Q45 of the master circuit 5 and the transistor Q46 of the slave circuit 6 which form a differential pair. I do. Further, in the configuration of the first embodiment, the clock signal CK
And transistors QL1 and QL6 each forming a current source circuit instead of transistors QL5 and QL6 forming a differential pair for switching a current path by clock complement signal CK.
5 and the resistor R26, and the transistor QL16 and the resistor R29. Therefore, the transistor QL1
1, QL12 or transistors QL13, QL14
Is always in an operating state regardless of the clock signal CK.

However, the differential pair (transistors Q41, Q42 and transistors Q43, Q43,
Q44) operates in response to the clock signal CK, and the relationship between the clock signal CK and the signal propagating between the differential pair thereof is the same as that of the first embodiment or the conventional circuit. The operation is the same as that of the first embodiment or the conventional circuit.

In the configuration of this embodiment, the current flowing through the data holding positive feedback circuit is also reduced by adopting a circuit configuration for separating the data reading circuit and the data holding positive feedback circuit including the current source circuit. The design can be made smaller than the current flowing in the data reading circuit. Therefore, the mirror capacitance Cm of the differential pair having positive feedback can be reduced, and the static flip-flop circuit can operate at high speed.

Further, by reducing the transistor size of the transistors QL11 to QL14 constituting the data holding positive feedback circuit, the mirror capacitance Cm is similarly reduced.
, And the static flip-flop circuit can be operated at high speed.

By the way, in the embodiment described above, an example in which a bipolar transistor is used as a transistor has been described. However, a static flip-flop circuit of the present invention can be similarly realized by using, for example, a GaAs MESFET. In this specification, a T-type flip-flop circuit capable of a frequency dividing operation has been described as an example of a flip-flop circuit. However, a D-type flip-flop circuit in which the output of a slave circuit is not fed back to the input of a master circuit is similarly used. The present invention can be applied to

[0029]

As described above, in the configuration of the static flip-flop circuit according to the present invention, the operating current and the transistor size of the differential pair having positive feedback are smaller than those of the other transistors. It is possible to reduce the size. Therefore, the mirror capacitance of the differential pair having the positive feedback can be reduced, the delay time when driving these transistors can be reduced, and the static flip-flop circuit can be operated at high speed.

Further, power consumption can be reduced by reducing the size of the transistor.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing the relationship between the maximum operating frequency obtained by SPICE simulation and the operating current of a differential pair having positive feedback for the circuit of the first embodiment.

FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 4 is a configuration example of a conventional static flip-flop circuit using an ECL basic circuit.

5 is a diagram illustrating the operation of the static flip-flop circuit shown in FIG.

[Explanation of symbols]

Q1 to Q18 Transistors R1 to R10 Resistors Q and Q output terminals Q21 to Q31 Transistors QL1 to QL7 Transistors R11 to R20 Resistors Q41 to Q51 Transistors QL11 to QL16 Transistors R21 to R31 Resistors

Claims (2)

(57) [Claims] 1. A static flip-flop circuit comprising two latch circuits, a master circuit and a slave circuit, each of which has a differential pair for reading data and a differential pair for holding data. The collector is connected to the common emitter of the upper differential pair for reading, and the collector is connected to the emitter of the first transistor whose base is supplied with a clock signal and the common emitter of the upper differential pair for reading data of the slave circuit. Connected to an emitter of a second transistor to which a clock complement signal is input to a base,
A first lower differential pair is formed for each upper differential pair, a first current source circuit is connected to a common emitter thereof, and a collector is connected to a common emitter of the upper differential pair for data retention of the master circuit. A collector is connected to the emitter of the third transistor whose base is supplied with a clock complement signal, and the collector is connected to the common emitter of the upper differential pair for holding data of the slave circuit. And a second current source circuit connected to a common emitter of the second lower differential pair for each upper differential pair. 2. A static flip-flop circuit comprising two latch circuits, a master circuit and a slave circuit, each of which has a differential pair for reading data and a differential pair for holding data. The collector is connected to the common emitter of the upper differential pair for reading, and the collector is connected to the emitter of the first transistor whose base is supplied with a clock signal and the common emitter of the upper differential pair for reading data of the slave circuit. Connected to an emitter of a second transistor to which a clock complement signal is input to a base,
A lower current differential pair is formed for each upper differential pair, a first current source circuit is connected to the common emitter, and a second current source circuit is connected to the common emitter of the data holding differential pair of the master circuit. A static flip-flop circuit, wherein a third current source circuit is connected to a common emitter of a data holding differential pair of the slave circuit.