JP3340142B2 - Dynamic frequency divider - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic frequency divider using a differential buffer circuit composed of MESFETs.

[0002]

2. Description of the Related Art In information communication systems and various measuring instruments that handle high-speed signals, many frequency dividers having excellent band characteristics are required. As an example of such an ultra-high-speed frequency divider, GaAs
A dynamic frequency divider using a MESFET is known.

FIG. 3 shows a configuration example of a conventional dynamic frequency divider. In this circuit, a two-stage differential buffer circuit using GaAs MESFETs is connected in a ring shape via a transfer gate, and a frequency-divided output is obtained by clock-controlling the transfer gate. FIG. 4 shows the clock signal waveform and the frequency divider output waveform.

FIG. 5 shows an operation region of the conventional dynamic frequency divider with respect to the clock bias voltage Vck and the frequency. Here, the clock bias voltage Vck is
As shown in FIG. 4, the "H" level of the clock CK and the "L" level
It is an intermediate level. The hatched area in FIG. 5 indicates an inoperable area. The conventional dynamic frequency divider shown in FIG. 3 has the following problem.

[0005] First, operation in the low frequency range is not possible. This is MESFET for transfer gate
Is off, between the source and gate,
This is because the leakage between gates is large. Originally, a dynamic frequency divider is used for a high frequency with respect to a static frequency divider using a flip-flop. However, considering the versatility of the frequency divider, it is desirable that the frequency divider can operate at a low frequency.

Second, the range of the operable clock bias voltage Vck changes depending on the frequency. FIG.
As shown in (2), as the frequency increases, the clock bias voltage Vck in the operable range increases. Therefore, the clock bias voltage Vck must be changed according to the frequency used. This is inconvenient for the user.

[0007]

As described above, the conventional dynamic frequency divider becomes inoperable in the low frequency range,
Another problem is that the clock bias voltage in the operable range changes depending on the frequency.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a dynamic frequency divider which can operate at a lower frequency than the conventional one and has a small frequency dependency of a clock bias voltage in an operable range. The purpose is to provide.

[0009]

A dynamic frequency divider according to the present invention has a differential circuit having a pair of driver MESFETs whose sources are commonly connected to a current source, and two outputs of the differential circuit. MESFET for source follower and MES for each source follower provided at each node
MESFE for pull-down provided on the source side of FET
A plurality of differential buffer circuits each including a source follower circuit having T are connected in a ring shape via a transfer gate. In such a configuration, the present invention provides two pull-down Ms in one source follower circuit among a plurality of differential buffer circuits.
The ESFET is characterized in that a gate and a drain are cross-connected to each other to form a flip-flop.

[0010]

According to the present invention, a flip-flop is formed by a pair of pull-down MESFETs in a differential buffer circuit and has a data latch function, so that it can operate even in a lower frequency region than before. become. In addition, as a result of improving the stability of data retention, the frequency dependence of the clock bias voltage in the operable range is reduced. Moreover, these performance improvements can be realized only by simple connection changes without adding new circuit elements to the conventional circuit.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows GaAs according to one embodiment of the present invention.
This is a dynamic frequency divider using MESFET. In this embodiment, two-stage differential buffer circuits 1 and 2 are used. Input / output nodes of these first and second differential buffer circuits 1 and 2 are connected to transfer gate MESFETs-Q41 and Q4 controlled by a clock signal CK.
2 and MESFET-Q31, Q32 for transfer gates controlled by the clock signal / CK. However, the connection relationship is set so that one of the first and second differential buffer circuits 1 and 2 functions as an inverter buffer.

The first differential buffer circuit 1 includes a driver MESFET-Q11, Q12 whose source is commonly connected to a current source consisting of a MESFET-Q13 and a resistor R14, and a difference comprising load resistors R11-R13. It is based on a motion circuit. A source follower circuit is provided at each of two output nodes of the differential circuit. The source follower circuit has a source follower MESFET-Q14, Q14 having a gate connected to each output node and a drain connected to the positive power supply potential.
15. These sources have level shift diodes LD11,
MESFET for pull-down connected via LD12-
Q16 and Q17 and pull-down resistors R15 and R16. In the figure, the level shift diode LD1
1 and the LD 12 are each configured by connecting four Schottky diodes in series, but the number is appropriately selected according to the circuit performance and the power supply potential. The level shift diodes LD11 and LD12 can be omitted.

The configuration of the second differential buffer circuit 2 is basically the same as that of the first differential buffer circuit 1. That is, MESFET-Q21, Q22 for drivers whose sources are commonly connected to a current source consisting of MESFET-Q23 and resistor R24.
And a differential circuit composed of load resistors R21 to R23. The two output nodes of the differential circuit are connected to source follower MESFETs-Q24 and Q25, level shift diodes LD21 and LD22, and pull-down MESFETs-Q26 and Q26.
27, and a source follower circuit constituted by pull-down resistors R25 and R26.

In this embodiment, of the two differential buffer circuits 1 and 2, two pull-down MESFETs-Q26 and Q27 in the second differential buffer circuit 2 are used.
However, a drain and a gate are cross-connected to each other to form a flip-flop.

The current source M of the first differential buffer circuit 1
ESFET-Q13, MESFET-Q16 for pull-down,
Q17, MESFE for the current source of the second differential buffer circuit 2
A fixed bias VB1 is applied to the gate of T-Q23.

The basic operation of this dynamic frequency divider is as follows.
It is no different from the conventional one. In brief, from the state where the differential output is OUT = “L” and / OUT = “H”,
When the clock signal CK rises, the transfer gate MESFETs = Q41 and Q42 are turned on, and the output of the first differential buffer circuit 1 is changed to the second differential buffer circuit 2
OUT = “H”, / OUT with a delay of one buffer from the rise of the clock signal CK
= “L”. Next, when the clock signal / CK rises, the transfer gate MESFETs-Q31 and Q32 are turned on, and the output data OUT and / OUT are transmitted to the first differential buffer circuit 1. Then, when the clock signal CK rises next, the transfer gate MESF
ET-Q41 and Q42 are turned on, the data inverted from the previous cycle is transmitted to the second differential buffer circuit 2, and the output is again delayed by one stage to OUT = “L”, / OU
T is inverted to “H”.

In this frequency dividing operation, in this embodiment, since the pull-down MESFETs-Q26 and Q27 in the source follower output section of the second differential buffer circuit 2 constitute a flip-flop, the outputs OUT and // OUT data is latched by this flip-flop. In other words, the output of the second differential buffer circuit 2 is static. Therefore, according to this embodiment, a stable frequency division operation can be performed even at an operation frequency lower than the conventional one.

FIG. 2 shows an operation range with respect to the clock bias voltage Vck and the frequency in the dynamic frequency divider of this embodiment. The specific circuit configuration conditions were as follows: all of the MESFETs used had a gate width of 54 μm,
The power supply potential was 0 V on the positive power supply side and -5.2 V on the negative power supply side. The operable frequency range in this embodiment is from 100 MHz to 12 GHz, and can operate up to a low frequency region where the conventional device does not operate normally. Further, as is apparent from comparison with FIG. 5, the frequency dependence of the operable clock bias voltage range is also reduced. The data measurement conditions in FIGS. 5 and 2 are only the difference between whether the pull-down MESFET of the second differential buffer circuit has a flip-flop configuration or a fixed bias. Further, this embodiment has an advantage that the above-described performance improvement is performed by simply changing the wiring connection without adding any new circuit element.

The present invention is not limited to the above embodiment. For example, in the embodiment, the flip-flop is configured in the second differential buffer circuit on the output terminal side as the frequency divider. However, the flip-flop may be configured in the first differential buffer circuit. The same effect can be obtained. In the embodiment, the frequency divider constituted by the two-stage buffer circuit has been described. However, the present invention can be similarly applied to the case where three or more buffer circuits are used. In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[0021]

As described above, according to the present invention, there is provided a dynamic frequency divider in which the operable range is extended to the low frequency region and the frequency dependency of the operable clock bias voltage range is reduced. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a dynamic frequency divider according to one embodiment of the present invention.

FIG. 2 is a diagram showing an operable range with respect to a clock bias voltage and a frequency in the embodiment.

FIG. 3 is a diagram showing a configuration of a conventional dynamic frequency divider.

FIG. 4 is a diagram showing operation waveforms of the frequency divider.

FIG. 5 is a diagram showing an operable range with respect to a clock bias voltage and a frequency of the frequency divider.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st differential buffer circuit, 2 ... 2nd differential buffer circuit, Q31, Q32, Q41, Q42 ... MES for transfer gates
FET, Q11, Q12, Q21, Q22 ... MESFET for driver, Q14, Q15, Q24, Q25 ... MESFE for source follower
T, Q16, Q17, Q26, Q27 ... pull-down MESFET, LD11, LD12, LD21, LD22 ... level shift diode, Q13, Q23 ... current source MESFET, R11-R13, R21, R23 ... load resistance, R14, R24 ... Current source resistors, R15, R16, R25, R26 ... pull-down resistors.

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kenji Ishida 1 Toshiba Research Institute, Komukai, Kawasaki City, Kanagawa Prefecture (56) References JP-A-3-121620 (JP, A) Hei 2-21723 (JP, A) JP-A-62-243353 (JP, A) JP-A-63-151117 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 23 / 00

Claims (1)

(57) [Claims] 1. A pair of drivers in which a plurality of stages of differential buffer circuits are connected in a ring via a transfer gate controlled by a clock, and wherein the differential buffer circuit has a common source connected to a current source. And a source follower circuit having a pull-down MESFET provided on the source side of each source follower MESFET provided at each of two output nodes of the differential circuit. In the dynamic frequency divider configured, two pull-down MESFETs in one source follower circuit among the plurality of differential buffer circuits have a gate and a drain cross-connected to each other to form a flip-flop. A dynamic frequency divider characterized by the following.