JPH06232663A - Variable gain amplifier - Google Patents

Abstract

PURPOSE:To provide a variable gain amplifier in which a bias of an output terminal is unchanged even when a control voltage is changed so as to facilitate the bias setting of an input control voltage and an input signal. CONSTITUTION:A differential amplifier comprising transistors(TRs) Q1, Q2, resistors RL1, RL2 and a current source J1 is provided with a bias circuit comprising a TRQ3, a resistor RL3 and a current source J2, a current of the current source J3 is changed by a control voltage to change a current supplied to the differential amplifier and the bias circuit, then the bias for the control voltage and for the input signal are set independently by making a bias at the output terminal constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier,
In particular, it relates to a variable gain amplifier of an automatic gain control circuit used in an integrated circuit.

[0002]

2. Description of the Related Art An example of a conventional variable gain amplifier is, for example, as shown in FIG. 3, a first differential pair composed of transistors Q23 and Q24 and a second differential pair composed of transistors Q25 and Q26. A bi-differential pair that receives the configured gain control voltage is provided, and includes transistors Q21 and Q22 and resistors RE21 and RE22 inserted in the emitter,
It has a configuration in which the collectors of a third differential pair, which receive signals v of different polarities as inputs to their respective bases, are connected to the respective common emitters of the bi-differential pair.

The resistors RE21 and RE22 connected to the emitter of the third differential pair are connected to each other and also to the current source J21 of the constant current I0, and the output signal v0 is inserted into the collector of the bi-differential pair. It is taken out from the resistor RL21. In the variable gain amplifier of FIG. 3, when biased, the currents flowing through the respective collectors of the bi-differential pair of transistors Q23, Q24, Q25, Q26 are equal to each other.

Here, the voltage difference between the control voltages input to the input terminals 21 and 22 changes by VA, and the transistor Q2
Assuming that the ratio of the current IQ23 flowing in 3 to the current IQ24 flowing in the transistor Q24 becomes A: 1, the voltage gain GV of the variable gain amplifier of FIG.
Assuming 0, the following equation is obtained.

GV = RL / (re + RE) · A / (1 + A) where A = exp (Q | VA | / (KT)), re =
Since KT / Q / (I0 / 2), the gain can be changed by changing the control voltage. However, K is a Boltzmann's constant, Q is an elementary charge of an electron, and T is a junction temperature. Further, if the bias potential of the output terminal 23 at this time is VBout, the current value of the current source J21 is I0, and the voltage of the power source 24 is Vcc, the following equation is obtained.

VBout = Vcc-RL.multidot.I0 / 2.multidot.A / (1 + A) FIG. 4 is a circuit diagram showing another example of the conventional variable gain amplifier. In FIG. 4, another example of the conventional variable gain amplifier is a first bi-difference composed of a first differential pair composed of transistors Q33 and Q34 and a second differential pair composed of transistors Q35 and Q36. And a collector of each of a third differential pair of transistors Q31, Q32 connected to the common emitter of each of the first bi-differential pair, and a fourth difference of transistors Q39, Q40. Has a second bi-differential pair composed of a dynamic pair and a fifth differential pair composed of transistors Q41 and Q42, each of which has a common emitter composed of transistors Q37 and Q38. Sixth
The collectors of the differential pairs are connected.

The common emitter of the first differential pair is connected to the first current source J31, and the emitters of the sixth differential pair are both connected to the second current source J via resistors RE31 and RE32.
In the transistor which is connected to 32 and constitutes the first and second bi-differential pairs, the collectors of the transistors Q33 and Q41 are respectively connected, the collectors of the transistors Q34 and Q42 are respectively connected, and the collectors of the transistors Q35 and Q39 are connected. Are respectively connected, and collectors of the transistors Q36 and Q40 are respectively connected. The output signal is taken out from the load resistor RL33 connected to the common collector of the transistors Q35 and Q39 of the first and second bi-differential pairs. A control voltage is input to the first and second bi-differential pairs, signals v having different polarities are input to the bases of the sixth differential pair, and the third differential pair is input. Is applied with the same bias voltage VB as the bias voltage VB applied to the sixth differential pair. In the circuit of FIG. 4, the first,
The voltage difference between the control voltages input to the input terminals 31 and 32 of the second bi-differential pair changes by VA,
Assuming that the ratio of the current IQ39 flowing through the transistor IQ40 to the current IQ40 flowing through the transistor Q40 becomes A: 1, the voltage gain GV of the variable gain amplifier of FIG.
When set to 0, the following equation is obtained.

GV = RL / (re + RE) · A / (A + 1) where A = exp (Q | VA | / (KT)), re =
Since KT / Q / (I0 / 2), the gain can be changed by changing the control voltage. However, K is a Boltzmann's constant, Q is an elementary charge of an electron, and T is a junction temperature. Set the bias potential of the output terminal 33 to VBou
t, the current value of the current sources J31 and L32 is I0, and the voltage of the power source 34 is Vcc, the following equation is obtained.

VBout = Vcc-RL.multidot.I0 / 2

In the conventional variable gain amplifier of FIG. 3, the bias potential VBout of the output terminal is as follows, as already described.

VBout = Vcc-RL.multidot.I0 / 2.multidot.A / (1 + A) A = exp (Q | VA | / (KT)) Since the bias potential of the output changes when the control voltage changes, it is applied to an integrated circuit. In such a case, the connection to the next stage is often a direct connection, and a large margin for the change in the input bias of the next stage must be expected, which is inconvenient when the power supply voltage has no margin. In order to improve this drawback, a variable gain amplifier as shown in FIG. 4 has been devised,
As described above, the bias potential of the output terminal 33 can be made constant regardless of the control voltage. However, there is a parasitic capacitance in the collector of the planar transistor used in the integrated circuit. In the variable gain amplifier of FIG. 4, the number of collectors of the transistors connected to the load resistance is twice that of the variable gain amplifier of FIG. 3, and the parasitic capacitance is also doubled. If it is dominant, there is a drawback that the frequency characteristic is deteriorated to about half.

Further, in FIG. 3, for example, the transistor Q2
1 and Q23, and in FIG. 4, for example, transistors Q31 and Q3
In the conventional variable gain amplifier as shown in No. 3, the differential pair is connected in two stages, and the bias of each transistor cannot be set independently. Therefore, it is difficult to set the bias.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a variable gain amplifier which makes the bias voltage constant and does not reduce the frequency characteristic.

[0013]

The variable gain amplifier according to the present invention is provided with a first differential amplifier circuit including first and second transistors to which input signals are supplied to respective bases. , The emitters of the first and second transistors are commonly connected via first and second resistors,
The collectors of the first and second transistors are commonly connected through the third and fourth resistors, respectively, and are also connected to the emitter of the third transistor, and the collector of the third transistor is the first power supply. The base of the third transistor is connected to the first power source through a fifth resistor, and the first and second control voltages are supplied to the respective bases of the fourth, fifth and A second differential amplifier circuit composed of sixth and seventh transistors is provided, and the emitters of the fourth, fifth, sixth and seventh transistors are commonly connected and serve as a first current source. Connected, the collectors of the sixth and seventh transistors are commonly connected,
The collector of the fourth transistor is connected to the second power supply, and the current supplied to the first differential amplifier circuit is changed by the current flowing through the common collector of the sixth and seventh transistors, The current supplied to the resistor 5 is variable by the collector current of the fifth transistor.

[0014]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a variable gain amplifier according to the first embodiment of the present invention. In FIG. 1, the present embodiment has a differential pair including transistors Q1 and Q2 and an emitter resistor RE.
1, RE2, load resistors RL1 and RL2, and a first current source J1, a differential amplifier that receives the signal v, a second current source J2, resistors RL3 and RB, and a transistor Q3. And a differential pair that receives a control voltage and sends out a current to the current sources J1 and J2. The differential pair includes transistors Q4, Q5, Q
6 and Q7, and the collectors of the transistors Q6 and Q7 are commonly connected. The bias circuit is
Connected to the load resistors RL1 and RL2 of the differential amplifier,
The resistors RL1, RL2 and RL3 are selected to have the same resistance value.

Next, the operation will be described. If the control voltage input to the input terminal 1 from the biased state changes by VA from the voltage input to the input terminal 2, the current values of the current sources J1, J2 and J3 are I0,
As for I1 and I2, the current IA flowing through the common collector of the transistors Q6 and Q7 and the current IB flowing through the collector of the transistor Q5 are respectively expressed by the following equations.

IA = I2 · A / (1 + A) IB = I2 / 2 / (1 + A) where A = exp (Q | VA | / (KT)) and K
Is the Boltzmann's constant, Q is the elementary charge of the electron, and T is the junction temperature.

The voltage of the power supply 4 is set to Vcc. Transistor Q3
When the base-emitter potential of VBEQ3 is VBEQ3, the bias potential VBout of the output terminal 3 is VBout = Vc
c-VBEQ3-RL3I1-RL1I0 / 2 + I2 /
It becomes 2 / (1 + A) * (RL3 + ARL1). Resistance R
If the values of L1, RL2, and RL3 are chosen to be RL, VB
out = Vcc-VBEQ3-RL (I1 + I0 / 2-
Even if the control voltage is input to the input terminals 1 and 2, the bias voltage of the output terminal 3 can be kept constant. The resistor RB causes a voltage drop to the extent that the transistors Q6 and Q7 are not saturated. Also, the voltage gain G
V becomes the following formula.

GV = RL / (re + RE) where re = KT / Q / ((I0-I2.A / (1+
A)) / 2), A = exp (Q | VA | / (KT)).

On the other hand, the number of collectors of the transistors connected to the load resistor RL1 is one, and the parasitic capacitance entering the load resistor is similar to that of the conventional example of FIG. Further, a differential pair composed of transistors Q4, Q5, Q6, Q7 and having a control voltage as an input, and a transistor Q
The bias of the differential amplifier composed of 1 and Q2 and receiving the signal v can be set independently.

FIG. 2 is a circuit diagram of the second embodiment of the present invention. In FIG. 2, the second embodiment is a transistor Q.
A differential pair composed of 11, Q12 and an emitter resistor RE1
1, RE12, load resistors RL11 and RL12, and a first current mirror including transistors Q18 and Q19, and a differential amplifier that receives the signal v is provided.
A second current mirror composed of transistors Q10 and Q20, a bias circuit composed of a resistor RL13 and a transistor Q13, and a differential pair which receives a control voltage as an input and supplies the currents of the first and second current mirrors. Have.

The differential pair includes transistors Q14 and Q1.
5, Q16, Q17, and transistors Q16, Q
17 collectors are commonly connected, and transistor Q14,
The emitters of Q15, Q16 and Q17 are connected in common and connected to the current source J11. The bias circuit includes load resistors RL11 and R of the differential amplifier.
Is connected to L12 and has resistors RL11, RL12, RL13
Are chosen to be the same value.

Next, the operation will be described. Assuming that the control voltage input to the input terminal 11 from the biased state changes by VA from the voltage input to the input terminal 12, if the current value of the current source J11 is I0, the transistors Q16 and Q17 have the same value. Current I flowing through the collector
A, current IB flowing through the collector of transistor Q15
Are respectively the following equations.

IA = I0 · A / (1 + A) IB = I0 / 2 / (1 + A) where A = exp (Q | VA | / (KT)), K is Boltzmann's constant, Q is elementary charge of electron, T is a junction temperature, and when the voltage of the power supply 14 is Vcc and the base-emitter potential of the transistor Q13 is VBEQ13, the bias potential VBout of the output terminal 13 is VBout = Vc.
c-VBEQ13-I0 / 2 / (1 + A) (RL3 + A
・ RL1). If the resistors RL1, RL2, and RL3 have the same value RL, VBout = Vcc-VBEQ1
Even if the control voltage is input to the input terminals 11 and 12, the bias voltage of the output terminal 13 can be kept constant. The voltage gain GV is given by the following equation.

GV = RL / (re + RE) where re = KT / Q / (I0 · A / (1 + A)) /
2), A = exp (Q | VA | / (KT)).

The frequency characteristic and the bias voltage setting are the same as those of the embodiment of FIG. 1, but the embodiment of FIG. 2 can be realized with a smaller number of elements than the embodiment of FIG.

[0026]

As described above, the variable gain amplifier of the present invention has the effects that the output bias voltage can be kept constant and the frequency characteristics are not deteriorated.

As an example, the collector-emitter voltage required to prevent the transistor from being saturated is 1V,
It is assumed that the base-emitter voltage of the transistor is 0.8 V, and a current mirror is usually used as the current source, so that the required voltage is about 1 V. Furthermore, output amplitude is 1V
In the conventional example of FIG. 3, the bias setting range of the control voltage is (2.8 V to Vcc-1.2 V),
The bias setting range of the input signal is (1.8 V to Vcc-
2.2V). On the other hand, in the variable gain amplifier of the present invention shown in FIG. 2, the bias setting range of the control voltage is (0.8 V to V).
cc-1.8V), and the bias setting range of the input signal is (1.8V to Vcc-2.2V), the range of bias setting is widened, and the control voltage and the bias of the input signal can be set independently. is there. Since the bias of the control signal and the bias of the input signal can be set independently, the bias can be easily set, and the variable gain amplifier having an easy design can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a variable gain amplifier according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an example of a conventional variable gain amplifier.

FIG. 4 is a circuit diagram of another example of a conventional variable gain amplifier.

[Explanation of symbols]

1, 2, 11, 12, 21, 22, 31, 32 Input terminal 3, 13, 23, 33 Output terminal 4, 14, 24, 34 Power supply RE1, RE2, RE11, RE12, RE22, RE
31, RE32 Emitter resistance RL1, RL2, RL3, RL11, RL12, RL1
3, RL21, RL22, RL31, RL32, RL3
3, RL34 Load resistance Q1 to Q7, Q10 to Q26, Q31 to Q42 Transistors J1 to J3, J11, J21, J31, J32 Current source VB Bias voltage v Signal

Claims (3)

[Claims] 1. A first differential amplifier circuit comprising first and second transistors to which an input signal is supplied to respective bases is provided, and the emitters of the first and second transistors are respectively the first , And are commonly connected via a second resistor, and the collectors of the first and second transistors are commonly connected via third and fourth resistors, respectively, and are also connected to the emitter of a third transistor. , The collector of the third transistor is connected to the first power supply, the base of the third transistor is connected to the first power supply via a fifth resistor, and the first and second control voltages are A second differential amplifier circuit including fourth, fifth, sixth and seventh transistors supplied to respective bases is provided, and the emitters of the fourth, fifth, sixth and seventh transistors are provided. Are commonly connected To a first current source, the collectors of the sixth and seventh transistors are commonly connected, the collector of the fourth transistor is connected to a second power supply, and the first differential amplifier circuit is connected. Is varied by the current flowing through the common collector of the sixth and seventh transistors, and the current supplied to the fifth resistor is varied by the collector current of the fifth transistor. Variable gain amplifier. 2. The collectors of the sixth and seventh transistors and the first and second resistors are connected to the second power supply via a second current source, and the third transistor is connected. Has a base connected to a third current source through a sixth resistor, a collector of the fifth transistor is connected to the third current source, and the third current source is connected to the second power source. The variable gain amplifier according to claim 1, which is connected. 3. The collectors of the sixth and seventh transistors and the first and second resistors are connected to a first current mirror, and the collectors of the fifth transistor and the fifth resistor are connected. The variable gain amplifier according to claim 1, wherein is connected to the second current mirror.