JPH0563557A - Dynamic frequency divider - Google Patents

Abstract

PURPOSE:To enable the operation up to a low frequency by constituting flip- flops of two pull-down MESFETs in one source follower circuit among plural differential buffer circuits while the gate and the drain are connected in crossing. CONSTITUTION:The configuration of a 2nd differential buffer circuit 2 is basically similar to that of 1st differential buffer circuit. That is, a differential circuit consisting of driver MESFETs Q21, Q22 whose source are connected in common to a current source comprising a MESFET Q23 and a resistor R24 and of load resistors R21-R23 is used for a basic circuit. Furthermore, drains and gates of two pull-down MESFETs Q26, Q27 in the circuit 2 are connected in crossing to form a flip-flop. The basic operation of the frequency divider is unchanged from a conventional frequency divider and since the flip-flop is constituted of the TRs Q26, Q27, that is, the frequency divider is made to be a static circuit, stable operation is enabled even at a low frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic frequency divider using a differential buffer circuit composed of MESFETs.

[0002]

2. Description of the Related Art In information communication systems handling various kinds of high speed signals and various measuring instruments, many frequency dividers having excellent band characteristics are required. As an example of such an ultra-high-speed frequency divider, GaAs
A dynamic frequency divider using MESFET is known.

FIG. 3 shows a structural example of a conventional dynamic frequency divider. In this circuit, a two-stage differential buffer circuit using GaAs MESFETs is connected in a ring shape via a transfer gate, and the transfer gate is clock-controlled to obtain a frequency-divided output. FIG. 4 shows the clock signal waveform and the frequency divider output waveform.

FIG. 5 shows the operating region with respect to the clock bias voltage Vck and the frequency of this conventional dynamic frequency divider. Here, the clock bias voltage Vck is
As shown in FIG. 4, "H" level and "L" of clock CK
It is the intermediate value of the level. The shaded area in FIG. 5 indicates an inoperable area. The conventional dynamic frequency divider shown in FIG. 3 has the following problems.

First, it is impossible to operate in the low frequency region. This is MESFET for transfer gate
Even if is off,
This is because the leak between the gates is large. Originally, the dynamic type frequency divider is used for high frequencies as compared with the static type frequency divider using a flip-flop, but it is desirable to be able to operate up to a low frequency considering the versatility of the frequency divider.

Second, the range of operable clock bias voltage Vck changes depending on the frequency. Figure 5
As shown in, the clock bias voltage Vck in the operable range becomes higher as the frequency becomes higher. Therefore, the clock bias voltage Vck must be changed according to the used frequency. This is inconvenient for the user.

[0007]

As described above, the conventional dynamic frequency divider becomes inoperable in the low frequency region,
There is also a problem that the clock bias voltage in the operable range changes depending on the frequency.

The present invention has been made in view of the above points, and provides a dynamic frequency divider capable of operating up to a lower frequency than before and having a small frequency dependency of the clock bias voltage in the operable range. The purpose is to provide.

[0009]

A dynamic frequency divider according to the present invention includes a differential circuit having a pair of driver MESFETs whose sources are commonly connected to a current source, and two outputs of the differential circuit. Source follower MESFETs and respective source follower MESs provided in the node
Pull-down MESFE provided on the source side of the FET
A plurality of stages of differential type buffer circuits composed of a source follower circuit having T are used, and these are connected in a ring shape via transfer gates. According to the present invention having such a configuration, two pull-down M's in one source follower circuit among a plurality of differential buffer circuits are provided.
The ESFET is characterized in that its gate and drain are cross-connected to each other to form a flip-flop.

[0010]

According to the present invention, since a flip-flop is constituted by a pair of pull-down MESFETs in the differential type buffer circuit and a data latch function is provided here, it is possible to operate even in a low frequency region as compared with the prior art. become. Further, as a result of improving the stability of data retention, the frequency dependency of the clock bias voltage in the operable range is also relaxed. Moreover, these performance improvements can be realized by simply changing the connection without adding new circuit elements to the conventional circuit.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows GaAs according to an embodiment of the present invention.
It is a dynamic frequency divider using MESFET. In this embodiment, two stages of differential buffer circuits 1 and 2 are used. The input / output nodes of the first and second differential buffer circuits 1 and 2 are transfer gate MESFETs-Q41 and Q4 controlled by the clock signal CK.
2 and the transfer gate MESFETs Q31 and Q32 controlled by the clock signal / CK. However, the connection relationship is set so that one of the first and second differential buffer circuits 1 and 2 serves as an inverter buffer.

The first differential type buffer circuit 1 has a difference between load resistors R11 to R13 and driver MESFETs-Q11 and Q12 whose sources are commonly connected to a current source consisting of MESFET-Q13 and resistor R14. It is based on a dynamic circuit. A source follower circuit is provided at each of the two output nodes of the differential circuit. The source follower circuit has a gate connected to each output node and a drain connected to a positive power supply potential, and is a source follower MESFET-Q14, Q.
15. Level shift diode LD11,
Pull-down MESFET connected via LD12-
It is composed of Q16, Q17 and pull-down resistors R15, R16. In the figure, the level shift diode LD1
1 and LD12 each show a case in which four Schottky diodes are connected in series, but the number is appropriately selected according to the circuit performance and the power supply potential. The level shift diodes LD11 and LD12 can be omitted.

The structure of the second differential type buffer circuit 2 is basically the same as that of the first differential type buffer circuit 1. That is, the sources are commonly connected to a current source composed of MESFET-Q23 and resistor R24, and driver MESFETs-Q21 and Q22.
And a load resistance R21 to R23. At the two output nodes of the differential circuit, source follower MESFETs-Q24, Q25, level shift diodes LD21, LD22, and pull-down MESFETs-Q26, Q.
27, and a source follower circuit constituted by pull-down resistors R25 and R26.

In this embodiment, of the two differential buffer circuits 1 and 2, two pull-down MESFETs-Q26 and Q27 in the second differential buffer circuit 2 are used.
, But the drains and gates of the two are cross-connected to form a flip-flop.

M for current source of the first differential type buffer circuit 1
ESFET-Q13, pull-down MESFET-Q16,
Q17, MESFE for current source of second differential buffer circuit 2
A fixed bias VB1 is applied to the gate of T-Q23.

The basic operation of this dynamic frequency divider is
It is the same as the conventional one. Briefly, from the state where the differential output is OUT = "L", / OUT = "H",
When the clock signal CK rises, the transfer gate MESFETs = Q41 and Q42 are turned on, and the outputs of the first and the differential type buffer circuit 1 are changed to the second differential type buffer circuit 2
Is transmitted to the output terminal, and OUT = “H”, / OUT with a delay of one stage from the rising edge of the clock signal CK.
= “L”. Next, when the clock signal / CK rises, the transfer gate MESFETs-Q31, Q32 are turned on, and the output data OUT, / OUT are transmitted to the first differential type buffer circuit 1. Then, when the clock signal CK rises next, the MESF for transfer gate
ET-Q41 and Q42 are turned on, the data inverted from the previous cycle is transmitted to the second differential type buffer circuit 2, and the output is also delayed by one stage, OUT = “L”, / OU.
Invert to T = “H”.

In this frequency division operation, in this embodiment, since the pull-down MESFETs-Q26 and Q27 at the source follower output section of the second differential type buffer circuit 2 form a flip-flop, the output OUT, / The data of OUT is latched in this flip-flop. In other words, the output part of the second differential buffer circuit 2 is static. Therefore, according to this embodiment, a stable frequency division operation can be performed even at an operating frequency lower than the conventional one.

FIG. 2 shows the operating range with respect to the clock bias voltage Vck and the frequency in the dynamic frequency divider of this embodiment. The specific circuit configuration condition is that all the MESFETs used have a gate width of 54 μm,
It was a D type with a threshold voltage of -0.2 V, and the power supply potential was 0 V on the positive power supply side and -5.2 V on the negative power supply side. The operable frequency range in this embodiment is 100 MHz to 12 GHz, and it is possible to operate in a low frequency region where the conventional one does not normally operate. Further, as is clear from comparison with FIG. 5, the frequency dependency of the operable clock bias voltage range is also small. Note that the data measurement conditions in FIG. 5 and FIG. 2 differ only in whether the pull-down MESFET of the second differential buffer circuit has a flip-flop configuration or a fixed bias. In addition, this embodiment has an advantage that the above-mentioned performance improvement is performed by simply changing the wiring connection without adding any new circuit element.

The present invention is not limited to the above embodiment. For example, in the embodiment, the flip-flop is configured in the second differential buffer circuit on the output terminal side as the frequency divider, but the flip-flop may be configured in the first differential buffer circuit. Also has exactly the same effect. Further, in the embodiment, the frequency divider composed of two stages of buffer circuits has been described, but the present invention can be similarly applied to the case where three or more stages of buffer circuits are used. Others The present invention can be variously modified and implemented without departing from the spirit of the invention.

[0021]

As described above, according to the present invention, there is provided a dynamic frequency divider in which the operable range is extended to a low frequency region and the operable clock bias voltage range has a small frequency dependency. be able to.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a dynamic frequency divider according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operable range with respect to a clock bias voltage and a frequency according to the embodiment.

FIG. 3 is a diagram showing a configuration of a conventional dynamic frequency divider.

FIG. 4 is a diagram showing operation waveforms of the frequency divider.

FIG. 5 is a diagram showing an operable range with respect to a clock bias voltage and a frequency of the frequency divider.

[Explanation of symbols]

1 ... 1st differential type buffer circuit, 2 ... 2nd differential type buffer circuit, Q31, Q32, Q41, Q42 ... MES for transfer gates
FET, Q11, Q12, Q21, Q22 ... MESFET for driver, Q14, Q15, Q24, Q25 ... MESFE for source follower
T, Q16, Q17, Q26, Q27 ... Pull-down MESFET, LD11, LD12, LD21, LD22 ... Level shift diode, Q13, Q23 ... Current source MESFET, R11-R13, R21, R23 ... Load resistance, R14, R24 ... Resistors for current source, R15, R16, R25, R26 ... Pull down resistors.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenji Ishida 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Research Institute

Claims (1)

[Claims] 1. A pair of drivers in which a plurality of stages of differential buffer circuits are connected in a ring shape via transfer gates that are clock-controlled, and the sources of the differential buffer circuits are commonly connected to a current source. Circuit having a source MESFET for a source follower provided at each of two output nodes of the differential circuit and a source follower circuit having a pull-down MESFET provided on the source side of each source follower MESFET In the configured dynamic frequency divider, the two pull-down MESFETs in one source follower circuit among the plurality of differential buffer circuits have gates and drains cross-connected to each other to form a flip-flop. Dynamic type frequency divider featuring.