JPS5928817U - signal generator - Google Patents
signal generatorInfo
- Publication number
- JPS5928817U JPS5928817U JP12290682U JP12290682U JPS5928817U JP S5928817 U JPS5928817 U JP S5928817U JP 12290682 U JP12290682 U JP 12290682U JP 12290682 U JP12290682 U JP 12290682U JP S5928817 U JPS5928817 U JP S5928817U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- pulse train
- storage device
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はＰＬＬ回路を用いた信号発生装置の従来例、第
２図は本考案の実施例、第３図は本考案の信号発生装置
の転用例である。
１・・・ピッチ抽出回路、２・・・位相検波回路、３゜
９・・・ＬＰＦ、 ４・・・ｖｃｏ、５・・・分周回路
、６・・・カウンタ、７・・・記憶装置、８＝・−Ｄ／
Ａ変換器、１０・・・パルス発振器、１１・・・ラッチ
、１２・・・分周回路、１３・・・遅延回路、１４・・
・エンベロープ検出回路、１５・・・本考案信号発生装
置、１６・・・ＰＬＬ回路、１７−ＶＣＡ０FIG. 1 shows a conventional example of a signal generating device using a PLL circuit, FIG. 2 shows an embodiment of the present invention, and FIG. 3 shows an example of a diversion of the signal generating device of the present invention. DESCRIPTION OF SYMBOLS 1... Pitch extraction circuit, 2... Phase detection circuit, 3°9... LPF, 4... VCO, 5... Frequency division circuit, 6... Counter, 7... Storage device , 8=・−D/
A converter, 10... Pulse oscillator, 11... Latch, 12... Frequency divider circuit, 13... Delay circuit, 14...
- Envelope detection circuit, 15... signal generator of the present invention, 16... PLL circuit, 17-VCA0
Claims (1)
信号の１周期間における第１のパルス列のパルス数をカ
ウントする第１の計数器と、前記計数器の計数値を分周
比とするとともに前記第２のパルス列を入力とする分周
器と、前記分周器の出力パルスをカウントする第２の計
数器と、前記第２の計数器の出力をアドレス信号とする
記憶装置と、前記記憶装置の出力をアナログ信号に変換
するディジタル−アナログ変換手段とを備え、前記第１
のパルス列に対する第２のパルス列の周波数！ｒ＋を前
記記憶装置に記憶されたデータワード数と等しくしたこ
とを特徴とする信号発生装置。generating means for generating first and second pulse trains; a first counter for counting the number of pulses of the first pulse train during one cycle of the input signal; and a count value of the counter as a frequency division ratio. a frequency divider that receives the second pulse train as an input; a second counter that counts output pulses of the frequency divider; and a storage device that uses the output of the second counter as an address signal; digital-to-analog conversion means for converting the output of the storage device into an analog signal;
The frequency of the second pulse train for the pulse train of ! A signal generating device characterized in that r+ is equal to the number of data words stored in the storage device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12290682U JPS5928817U (en) | 1982-08-13 | 1982-08-13 | signal generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12290682U JPS5928817U (en) | 1982-08-13 | 1982-08-13 | signal generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5928817U true JPS5928817U (en) | 1984-02-22 |
Family
ID=30280750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12290682U Pending JPS5928817U (en) | 1982-08-13 | 1982-08-13 | signal generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5928817U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02261588A (en) * | 1989-03-31 | 1990-10-24 | Katsumi Takao | Method for utilizing waste |
-
1982
- 1982-08-13 JP JP12290682U patent/JPS5928817U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02261588A (en) * | 1989-03-31 | 1990-10-24 | Katsumi Takao | Method for utilizing waste |
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