JPS6392430U - - Google Patents
Info
- Publication number
- JPS6392430U JPS6392430U JP18712786U JP18712786U JPS6392430U JP S6392430 U JPS6392430 U JP S6392430U JP 18712786 U JP18712786 U JP 18712786U JP 18712786 U JP18712786 U JP 18712786U JP S6392430 U JPS6392430 U JP S6392430U
- Authority
- JP
- Japan
- Prior art keywords
- contents
- msb
- circuit
- clock pulse
- preset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Description
第１図は本考案のパルス列発生回路の第１の実
施例の構成を示す図、第２図は同、信号波形図、
第３図は同、第２の実施例の構成を示す図、第４
図は同、信号波形図、第５図は従来のパルス列発
生回路の構成を示す図、第６図は同、信号波形図
である。
８……クロツクパルス発生回路、９……シフト
レジスタ回路、１０……第１のインバータ回路、
１１……プログラマブルカウンタ回路、１２……
第２のインバータ回路、１３……ＮＯＲ回路、１
４……第１の出力端子、１５……第２の出力端子
、１６……Ｄ―フリツプフロツプ回路、１７……
第３のインバータ回路１８。
FIG. 1 is a diagram showing the configuration of a first embodiment of the pulse train generation circuit of the present invention, and FIG. 2 is a signal waveform diagram of the same,
FIG. 3 is a diagram showing the configuration of the second embodiment, and FIG.
5 is a diagram showing the configuration of a conventional pulse train generation circuit, and FIG. 6 is a signal waveform diagram of the same. 8... Clock pulse generation circuit, 9... Shift register circuit, 10... First inverter circuit,
11...Programmable counter circuit, 12...
Second inverter circuit, 13...NOR circuit, 1
4...first output terminal, 15...second output terminal, 16...D-flip-flop circuit, 17...
third inverter circuit 18;
Claims (1)
回路８と、入力データを上記クロツクパルス毎に
最も桁の小さいビツトＬＳＢから上位の桁へシフ
トして、その内容［Ｏｎ＋１ Ｏｎ Ｏｎ−１…
…Ｏ２ Ｏ１］を出力し、最も桁の大きいビツト
ＭＳＢ［Ｏｎ＋１］をリセツト信号とするシフト
レジスタ回路９と、当該シフトレジスタ回路９の
上記ＭＳＢ［Ｏｎ＋１］を除いた内容 ［Ｏｎ
Ｏｎ−１……Ｏ２ Ｏ１］がプリセツト入力Ｐ
１，Ｐ２……Ｐｎ−１，Ｐｎにそれぞれ入力され
、当該プリセツト値［Ｏ１ Ｏ２……Ｏｎ−１
Ｏｎ］を初期値として上記クロツクパルスをカウ
ントし、その内容［Ｑｎ Ｑｎ−１……Ｑ２ Ｑ
１］がフルカウント値になつた時点でキヤリー信
号を出力するプログラマブルカウンタ回路１１と
を具備し、上記キヤリー信号を出力パルスとして
取り出すとともに、上記キヤリー信号によつて上
記シフトレジスタ回路９の内容［Ｏｎ＋１ Ｏｎ
Ｏｎ−１……Ｏ２ Ｏ１］をシフトし、当該シ
フトされた内容のＭＳＢ［Ｏｎ＋１］を除いた内
容 ［Ｏｎ Ｏｎ−１……Ｏ２ Ｏ１］を上記プ
ログラマブルカウンタ回路１１にプリセツトする
ことを特徴とするパルス列発生回路。 A clock pulse generation circuit 8 generates a clock pulse, and the input data is shifted from the smallest bit LSB to the higher digit for each clock pulse, and the contents [On+1 On On-1...
...O2 O1] and uses the largest bit MSB[On+1] as a reset signal, and the contents of the shift register circuit 9 excluding the above MSB[On+1] [On
On-1...O2 O1] is the preset input P
1, P2...Pn-1, Pn, respectively, and the corresponding preset value [O1 O2...On-1
The above clock pulses are counted with [On] as the initial value, and the contents [Qn Qn-1...Q2 Q
1] is provided with a programmable counter circuit 11 that outputs a carry signal when the value [On+1 On
On-1...O2 O1] and preset the content [On On-1...O2 O1] excluding the MSB[On+1] of the shifted content into the programmable counter circuit 11. Pulse train generation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18712786U JPH0419853Y2 (en) | 1986-12-03 | 1986-12-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18712786U JPH0419853Y2 (en) | 1986-12-03 | 1986-12-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6392430U true JPS6392430U (en) | 1988-06-15 |
| JPH0419853Y2 JPH0419853Y2 (en) | 1992-05-07 |
Family
ID=31137315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18712786U Expired JPH0419853Y2 (en) | 1986-12-03 | 1986-12-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0419853Y2 (en) |
-
1986
- 1986-12-03 JP JP18712786U patent/JPH0419853Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0419853Y2 (en) | 1992-05-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6392430U (en) | ||
| JPS6392431U (en) | ||
| JPS59140520U (en) | electronic volume | |
| JPH0221824U (en) | ||
| JPS6367819U (en) | ||
| JPH03117947U (en) | ||
| JPS62188845U (en) | ||
| JPS6374829U (en) | ||
| JPS61160556U (en) | ||
| JPS6390323U (en) | ||
| JPS62203521U (en) | ||
| JPS60121332U (en) | 8-phase shift pulse generation circuit | |
| JPS5840941U (en) | analog to digital converter | |
| JPS61156315U (en) | ||
| JPS599638U (en) | Simple D/A converter | |
| JPS637995U (en) | ||
| JPS6059635U (en) | DA converter | |
| JPH02108147U (en) | ||
| JPS62135237U (en) | ||
| JPH02118374U (en) | ||
| JPS63108234U (en) | ||
| JPS62109522U (en) | ||
| JPS6374830U (en) | ||
| JPS6438853U (en) | ||
| JPS6181221U (en) |