JPS5928289A - バツフア記憶制御方式 - Google Patents

バツフア記憶制御方式

Info

Publication number
JPS5928289A
JPS5928289A JP57138099A JP13809982A JPS5928289A JP S5928289 A JPS5928289 A JP S5928289A JP 57138099 A JP57138099 A JP 57138099A JP 13809982 A JP13809982 A JP 13809982A JP S5928289 A JPS5928289 A JP S5928289A
Authority
JP
Japan
Prior art keywords
buffer
data
address
row
buffer storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57138099A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6141024B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Noriaki Hashimoto
橋本　紀明
Kanji Kubo
久保　完次
Chikahiko Izumi
泉　千賀彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57138099A priority Critical patent/JPS5928289A/ja
Priority to US06/519,699 priority patent/US4561071A/en
Publication of JPS5928289A publication Critical patent/JPS5928289A/ja
Publication of JPS6141024B2 publication Critical patent/JPS6141024B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP57138099A 1982-08-09 1982-08-09 バツフア記憶制御方式 Granted JPS5928289A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57138099A JPS5928289A (ja) 1982-08-09 1982-08-09 バツフア記憶制御方式
US06/519,699 US4561071A (en) 1982-08-09 1983-08-02 Storage system having buffer storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57138099A JPS5928289A (ja) 1982-08-09 1982-08-09 バツフア記憶制御方式

Publications (2)

Publication Number Publication Date
JPS5928289A true JPS5928289A (ja) 1984-02-14
JPS6141024B2 JPS6141024B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1986-09-12

Family

ID=15213922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57138099A Granted JPS5928289A (ja) 1982-08-09 1982-08-09 バツフア記憶制御方式

Country Status (2)

Country Link
US (1) US4561071A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5928289A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0749813A (ja) * 1990-03-29 1995-02-21 Matsushita Electric Ind Co Ltd キャッシュメモリの制御方式およびキャッシュタグメモリの制御方式

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750154A (en) * 1984-07-10 1988-06-07 Prime Computer, Inc. Memory alignment system and method
US5237671A (en) * 1986-05-02 1993-08-17 Silicon Graphics, Inc. Translation lookaside buffer shutdown scheme
JPH07120312B2 (ja) * 1987-10-07 1995-12-20 株式会社日立製作所 バッファメモリ制御装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4419746A (en) * 1980-10-14 1983-12-06 Texas Instruments Incorporated Multiple pointer memory system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0749813A (ja) * 1990-03-29 1995-02-21 Matsushita Electric Ind Co Ltd キャッシュメモリの制御方式およびキャッシュタグメモリの制御方式

Also Published As

Publication number Publication date
JPS6141024B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1986-09-12
US4561071A (en) 1985-12-24

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