JPS5925245A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5925245A
JPS5925245A JP13416582A JP13416582A JPS5925245A JP S5925245 A JPS5925245 A JP S5925245A JP 13416582 A JP13416582 A JP 13416582A JP 13416582 A JP13416582 A JP 13416582A JP S5925245 A JPS5925245 A JP S5925245A
Authority
JP
Japan
Prior art keywords
film
aluminum
wiring layer
sio2
patterning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13416582A
Other languages
Japanese (ja)
Inventor
Yoshiaki Tanimoto
谷本 芳昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13416582A priority Critical patent/JPS5925245A/en
Publication of JPS5925245A publication Critical patent/JPS5925245A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To inhibit a projection through heat treatment of an Al layer by continuously coating the upper section of a semiconductor substrate with an Al film and an inorganic insulating film, patterning the insulating film, thermally treating the whole at a high temperature and patterning a wiring layer consisting of the Al film. CONSTITUTION:The upper section of the semiconductor substrate 11 is coated with the Al film 12 and the SiO2 film 13. A resist film 14 is applied, only a wiring layer forming section is masked through patterning, and the SiO2 film 13 exposed is removed through dry etching. When the resist film 14 is removed and the whole is thermally treated, the Al projections S are formed in the Al film exposed. The surface is dry-etched while using the SiO2 film 13 as a mask, the Al film 12 is patterned, and the desired Al wiring layer is formed. The substrate 11 is heated, and a PSG film is applied.

Description

【発明の詳細な説明】 (a)発明の技術分野 本発明は半導体装置の製造方法のうち、特に半導体集積
回路(IC)表面に形成するアルミニウム配線層の形成
方法の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, particularly to an improvement in a method for forming an aluminum wiring layer formed on the surface of a semiconductor integrated circuit (IC).

(b)従来の技術と問題点 ICは多数の能動素子や受動素子が半導体基板に設けら
れて、これらの素子相互間は導電配線層で接続される。
(b) Prior Art and Problems In an IC, a large number of active elements and passive elements are provided on a semiconductor substrate, and these elements are connected to each other through conductive wiring layers.

この導電配電層としはアルミニウム(Al)膜が最も良
く用いられており、それはアルミニウムが電気伝導性が
極めて良く、且つ安価な材料であるからである。
An aluminum (Al) film is most often used as this conductive distribution layer because aluminum has extremely good electrical conductivity and is an inexpensive material.

このようなアルミニウム配線層には通常1%程度のシリ
コンなどを含んでいるが、その形成方法はスパツタ法又
は蒸着法で被着させた後、フォト′プロセスにてレジス
ト膜マスクを形成し、四塩化炭素(CCl4)ガスを用
いたドライエツチングによつて配線層にパターンニング
する。その後、アルミニウム配線層の結晶原子を整列さ
せて導電性を良くするために、400〜500℃の高温
度で熱処理がおこなわれる。また、このような高温熱処
理をおこなわなくても、アルミニウム配線層の上面を覆
う保護膜を被覆する際に、化学気相成長(CVD)法で
保護膜を被着すれば、アルミニウム配線層を有する半導
体基板を420℃程度に加熱して、この加熱処理が導電
性回復の役目をも兼ねる。このような保護膜は、当然絶
縁膜であり、例えば燐シリケートガラス(PSG)膜や
二酸化シリコン(SiO2)膜が用いられて、またこの
保護膜はアルミニウム配線層を多層に形成する場合には
、各層間絶縁膜として同じくPSG膜やSiO2膜を用
いている。
Such an aluminum wiring layer usually contains about 1% silicon, etc., and the method for forming it is to deposit it by sputtering or vapor deposition, then form a resist film mask in a photo process, and then The wiring layer is patterned by dry etching using carbon chloride (CCl4) gas. Thereafter, heat treatment is performed at a high temperature of 400 to 500° C. in order to align the crystal atoms of the aluminum wiring layer and improve conductivity. In addition, even if such high-temperature heat treatment is not performed, if a protective film is applied using chemical vapor deposition (CVD) when covering the top surface of an aluminum wiring layer, the aluminum wiring layer can be coated with a protective film. The semiconductor substrate is heated to about 420° C., and this heat treatment also serves to restore conductivity. Such a protective film is naturally an insulating film, for example, a phosphorous silicate glass (PSG) film or a silicon dioxide (SiO2) film is used, and when this protective film is formed with multiple aluminum wiring layers, Similarly, a PSG film or a SiO2 film is used as each interlayer insulating film.

ところが、アルミニウム配線層を高温熱処理して、結晶
原子を整列させると、結晶が異常成長して突起が生じ、
例えば膜厚1μmのアルミニウム配線に対し、長さ1μ
m近いアルミニウム突起が成長して、保護膜のカバレイ
ジ(coverage:被覆性)を悪くし、また多層配
線の場合には配線層間の絶縁性が悪くなるなど、信頼性
上危惧すべき問題が発生する。第1図はこのようなアル
ミニウム突起Sを示しており、半導体基板1上にアルミ
ニウム配線層2を形成し、その上にPSG膜3を被覆し
て生じたもので、突起部分でPSG膜がうすくなつてい
るから、水分などの浸入が容易となり、アルミニウムが
変質しやすい。
However, when the aluminum wiring layer is subjected to high-temperature heat treatment to align the crystal atoms, the crystals grow abnormally and protrusions form.
For example, for aluminum wiring with a film thickness of 1 μm, the length is 1 μm.
Aluminum protrusions that grow close to 3000 m in length deteriorate the coverage of the protective film, and in the case of multilayer wiring, the insulation between wiring layers deteriorates, causing problems in terms of reliability. . FIG. 1 shows such an aluminum protrusion S, which is generated by forming an aluminum wiring layer 2 on a semiconductor substrate 1 and covering it with a PSG film 3, and the PSG film is thin at the protrusion part. Because it is rusted, it is easy for moisture to enter, causing aluminum to deteriorate.

したがつて、このような問題点を除去するために、例え
ばアルミニウム膜を蒸着法で被着した後、ニ弗化ボロン
(BF2)イオンを高濃度に注入して、アルミニウム膜
の硬度を上げて突起が外部に成長しないようなイオン注
入処理がおこなわれている。
Therefore, in order to eliminate these problems, for example, after depositing an aluminum film by vapor deposition, boron difluoride (BF2) ions are implanted at a high concentration to increase the hardness of the aluminum film. Ion implantation processing is performed to prevent protrusions from growing externally.

しかしながら、高加速電圧で長時間(例えば100Ke
V,1時間)の処理をおとなうことは、それだけ時間と
工数の増加となる上に、余りにアルミニウム膜の硬度を
高くするこは、ワイヤーボンデングの際に接着強度を弱
くすることとなり、その面からまた信頼性上の問題が生
じる。
However, at high acceleration voltages and for long periods of time (e.g. 100Ke
Completing the process (V, 1 hour) increases time and man-hours accordingly, and increasing the hardness of the aluminum film too much weakens the adhesive strength during wire bonding. This also raises reliability issues.

(c)発明の目的 本発明は、このようなアルミニウム配線層の熱処理に伴
なうアルミニウム突起を抑制することを目的とする製造
方法を提案するものである。
(c) Object of the Invention The present invention proposes a manufacturing method for the purpose of suppressing aluminum protrusions caused by such heat treatment of an aluminum wiring layer.

(d)発明の構成 その目的は、半導体基板上にアルミニウム膜および無機
絶縁膜を連続して被着し、該無機絶縁膜をパターンニン
グして高温度熱処理し、次いで該無機絶縁膜をマスクと
して該アルミニウム膜からなる配線層をパターンニング
する工程が含まれてなる半導体装置の製造方法によつて
達成することができる。
(d) Structure of the Invention The purpose is to successively deposit an aluminum film and an inorganic insulating film on a semiconductor substrate, pattern the inorganic insulating film and heat treat it at high temperature, and then use the inorganic insulating film as a mask. This can be achieved by a method for manufacturing a semiconductor device that includes a step of patterning a wiring layer made of the aluminum film.

(e)発明の実施例 以下、図面を参照して実施例によつて詳細に説明する。(e) Examples of the invention Hereinafter, embodiments will be described in detail with reference to the drawings.

第2図ないし第6図は本発明にかゝる製造工程順断面図
で、先づ第2図で示すように半導体基板11上に連続ス
パツタ法によつて膜厚1μmの1%シリコンを含むアル
ミニウム膜12と膜厚1000〜2000Åのニ酸化シ
リコン(SiO2)膜13とを被着する。連続スパツタ
法とは、例えば第7図に示すようなRFスパツタ装置を
用いて、第1スパツタ室21ではアルミニウム膜をスパ
ツタし、第2スパツタ室22ではSiO2膜をスパツタ
して、それぞれの両側にロードロツク室23を設けて連
結しているため、大気中に曝すことなく連続して被着す
ることができる方法である。
2 to 6 are cross-sectional views of the manufacturing process according to the present invention. First, as shown in FIG. 2, a film of 1% silicon with a thickness of 1 μm is deposited on a semiconductor substrate 11 by a continuous sputtering method. An aluminum film 12 and a silicon dioxide (SiO2) film 13 having a thickness of 1000 to 2000 Å are deposited. The continuous sputtering method refers to sputtering an aluminum film in the first sputtering chamber 21 and sputtering an SiO2 film in the second sputtering chamber 22 using, for example, an RF sputtering device as shown in FIG. Since the load lock chamber 23 is provided and connected, this method allows continuous deposition without exposure to the atmosphere.

次いで、第3図に示すようにその上面にレジスト膜14
を塗布し、パターンニングして配線層形成部分のみマス
クした後、トリフロロメタン(CHF3)ガスを用いて
ドライエツチングによつて露出しているSiO2膜13
をエツチング除去する。次いで、第4図に示すようにレ
ジスト膜14を除去した後、窒素ガス(5%水素ガスを
含む)の雰囲気中で450℃、40分熱処理すると、露
出したアルミニウム膜表面にアルミニウム突起Sが生ず
る。この場合熱処理温度450℃は、以降の工程でPS
G膜を被着する際におこなう基板加熱温度420〜43
0℃より高い温度であり、まだスパツタしたアルミニウ
ムとシリコンとが合金化するに適した温度である。
Next, as shown in FIG. 3, a resist film 14 is formed on the upper surface.
After coating and patterning to mask only the portion where the wiring layer will be formed, the exposed SiO2 film 13 is dry etched using trifluoromethane (CHF3) gas.
Remove by etching. Next, as shown in FIG. 4, after removing the resist film 14, heat treatment is performed at 450° C. for 40 minutes in an atmosphere of nitrogen gas (containing 5% hydrogen gas), and aluminum protrusions S are formed on the exposed aluminum film surface. . In this case, the heat treatment temperature of 450°C is
Substrate heating temperature 420 to 43 when depositing G film
The temperature is higher than 0° C., which is suitable for alloying the still sputtered aluminum and silicon.

次いで、第5図に示すようにSiO2膜13をマスクと
して、CCl4とBCl3(三塩化ボロン)との混合ガ
スをエツチング剤としてドライエツチングをおこない、
アルミニウ膜12をパターンニングして、所望のアルシ
ミニム配線層にする。この工程では、従来のようにレジ
スト膜をマスクとしたアルミニウムのパターン形成とは
異なり、アルミニウム膜側面の虫喰い現象が発生しない
で、平滑な面の配線層が形成される。これは、レジスト
膜が存在すれば、CCl4ガスより塩酸ガスが生じてア
ルミニウム表面を腐蝕しやすく、レジスト膜がなければ
その反応が少ないためと考えられる。
Next, as shown in FIG. 5, using the SiO2 film 13 as a mask, dry etching is performed using a mixed gas of CCl4 and BCl3 (boron trichloride) as an etching agent.
The aluminum film 12 is patterned to form a desired aluminum wiring layer. In this process, unlike the conventional aluminum pattern formation using a resist film as a mask, a wiring layer with a smooth surface is formed without causing the worm-eaten phenomenon on the side surface of the aluminum film. This is considered to be because if a resist film is present, hydrochloric acid gas is generated more easily than CCl4 gas and corrodes the aluminum surface, and if there is no resist film, the reaction is less likely.

次いで、第6図に示すようにCVD装置(図示していな
い)に装入して、基板を420℃に加熱し、膜厚1μm
程度のPSG膜15を被着する。しかし、この加熱によ
つてアルミニウム突起の成長はおこらない。
Next, as shown in FIG. 6, the substrate is placed in a CVD apparatus (not shown) and heated to 420°C to form a film with a thickness of 1 μm.
A PSG film 15 of about 100 mL is deposited. However, this heating does not cause the growth of aluminum protrusions.

(f)発明の効果 上記実施例から判るように、本発明はSiO2膜のパタ
ーンニング工程増加とはなるが、長時間のイオン注入な
どの処理よりは工数が少なくて、アルミニウム突起の成
長が抑制され、しかも虫喰い状の表面が解消される効果
も加わつて、ICの信頼性向上に極めて寄与すうr方法
である。
(f) Effects of the Invention As can be seen from the above examples, although the present invention requires an additional process for patterning the SiO2 film, it requires fewer steps than a process such as long-term ion implantation, and the growth of aluminum protrusions is suppressed. In addition, this method greatly contributes to improving the reliability of ICs, as it also has the effect of eliminating moth-eaten surfaces.

尚、上記実施例は無機絶縁膜としてSiO2膜を例にと
つて説明したが、無機絶縁膜としてはその他に窒化シリ
コン(Si3N4)膜などがあり、それらを除外するも
のではない。
Although the above embodiments have been described by taking the SiO2 film as an example of the inorganic insulating film, other inorganic insulating films include silicon nitride (Si3N4) films and the like, and these are not excluded.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の問題点を示すアルミニウム配線層の断面
図、第2図ないし第6図は本発明にかゝる製造工程断面
図、第7図は連続スパツタ装置の概要図である。 図中、1,11は半導体基板、2、12はアルミニウム
膜、又はアルミニウム配線層、3、15はPSG膜、1
3はSiO2膜、14はレジスト膜、Sはアルミニウム
突起を示す。 第1図 第2図 第31ン1 第6図 第71川
FIG. 1 is a cross-sectional view of an aluminum wiring layer showing the conventional problems, FIGS. 2 to 6 are cross-sectional views of the manufacturing process according to the present invention, and FIG. 7 is a schematic diagram of a continuous sputtering apparatus. In the figure, 1 and 11 are semiconductor substrates, 2 and 12 are aluminum films or aluminum wiring layers, 3 and 15 are PSG films, 1
3 is a SiO2 film, 14 is a resist film, and S is an aluminum protrusion. Figure 1 Figure 2 Figure 31-1 Figure 6 71 River

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上にアルミニウム膜および無機絶縁膜を接続
して被着し、該無機絶縁膜をパターンニングして、高温
度熱処理し、次いで該無機絶縁膜をマスクとして該アル
ミニウム膜からなる配線層をパターンニングする工程が
含まれてなることを特徴とする半導体装置の製造方法。
An aluminum film and an inorganic insulating film are connected and deposited on a semiconductor substrate, the inorganic insulating film is patterned and subjected to high temperature heat treatment, and then a wiring layer made of the aluminum film is patterned using the inorganic insulating film as a mask. 1. A method for manufacturing a semiconductor device, the method comprising the step of:
JP13416582A 1982-07-30 1982-07-30 Manufacture of semiconductor device Pending JPS5925245A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13416582A JPS5925245A (en) 1982-07-30 1982-07-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13416582A JPS5925245A (en) 1982-07-30 1982-07-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5925245A true JPS5925245A (en) 1984-02-09

Family

ID=15121966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13416582A Pending JPS5925245A (en) 1982-07-30 1982-07-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5925245A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164339A (en) * 1988-09-30 1992-11-17 Siemens-Bendix Automotive Electronics L.P. Fabrication of oxynitride frontside microstructures
US5369053A (en) * 1989-10-24 1994-11-29 Hewlett-Packard Company Method for patterning aluminum metallizations
EP1168432A2 (en) * 2000-06-01 2002-01-02 Texas Instruments Incorporated Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164339A (en) * 1988-09-30 1992-11-17 Siemens-Bendix Automotive Electronics L.P. Fabrication of oxynitride frontside microstructures
US5369053A (en) * 1989-10-24 1994-11-29 Hewlett-Packard Company Method for patterning aluminum metallizations
EP1168432A2 (en) * 2000-06-01 2002-01-02 Texas Instruments Incorporated Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect

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