JPH01181533A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01181533A
JPH01181533A JP324188A JP324188A JPH01181533A JP H01181533 A JPH01181533 A JP H01181533A JP 324188 A JP324188 A JP 324188A JP 324188 A JP324188 A JP 324188A JP H01181533 A JPH01181533 A JP H01181533A
Authority
JP
Japan
Prior art keywords
film
plasma
substrate
wiring
coating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP324188A
Other languages
Japanese (ja)
Other versions
JP2883333B2 (en
Inventor
Shigehiko Kaji
成彦 梶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63003241A priority Critical patent/JP2883333B2/en
Publication of JPH01181533A publication Critical patent/JPH01181533A/en
Application granted granted Critical
Publication of JP2883333B2 publication Critical patent/JP2883333B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To prevent an occurrence of cracks to an insulating film by forming an insulation layer that covers a step on a substrate having a step, and by exposing an insulation layer to a gas plasma containing either nitrogen or O-based elements. CONSTITUTION:A first plasma CVD-SiO2 film 2 is formed on a substrate 6 in which wiring 1 is formed. On the entire surface of the substrate in which this film 2 is formed, an apply film forming solution is applied. The solution is evaporated, and a silicate-based compound film 3 is left on the substrate as an applied film. Following this, for example, hardening processing is performed in an oxygen plasma to form a silicate-based compound film 3a, and further a second plasma CVD-SiO2 film 4 is formed as an insulation film between layers. On it, wiring 5 is formed. Exposing insulation layers 2. 4 whose steps are coated to plasma enables the surfaces of insulation layers 2, 4 to be planarized at low temperatures, and for a hardening processing of the applied film 3, reaction can the promoted in a plasma at a low temperature. This makes it possible to prevent occurrences of cracks to an insulation layer or line disconnections of a wiring layer.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体装置の製造方法に係わり、特に基板に
形成された配線等の段差部を被覆する絶縁膜の平坦化の
方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor device, and in particular, the present invention relates to a method for manufacturing a semiconductor device, and in particular, a method for flattening an insulating film covering a stepped portion such as a wiring formed on a substrate. Regarding the method.

(従来の技術) 、  半導体装置の製造にあたり、通常、半導体素子あ
るいは配線上には他の領域と絶縁性を保つために絶縁膜
を形成する。この場合、前記配線や半導体素子は通常、
段差を有しているので、前記配線や半導体素子を被覆し
た絶縁膜表面は凹凸となる。前記絶縁膜の凹凸のうち特
に、角部では、他の部分に比べてストレスが多くかかり
、このため前記絶縁膜にクラックが生じる等、絶縁性を
保てなくなるという問題が生じることがある。
(Prior Art) In manufacturing a semiconductor device, an insulating film is usually formed on a semiconductor element or wiring to maintain insulation from other regions. In this case, the wiring and semiconductor elements are usually
Since there are steps, the surface of the insulating film covering the wiring and the semiconductor element becomes uneven. Among the irregularities of the insulating film, particularly at the corners, more stress is applied than to other parts, which may cause problems such as cracks in the insulating film and failure to maintain insulation properties.

特に、この問題は、近年半導体装置の大容量化・高集積
化に伴い用いられる多層配線構造のものにおいて顕著で
ある。つまり、前記多層配線構造の半導体装置を形成す
る場合、配線層と層間絶縁膜を繰り返し積層して形成す
るがその繰り返しによって段差は急峻となり、前記絶縁
膜に物理的なストレスが多くかかる。又、場合によって
は配線の方に断線を生じることもある。
This problem is particularly noticeable in multilayer wiring structures that have been used in recent years as semiconductor devices have become larger in capacity and more highly integrated. That is, when forming a semiconductor device with the multilayer interconnection structure, wiring layers and interlayer insulating films are repeatedly laminated, and due to the repetition, steps become steep, and a large amount of physical stress is applied to the insulating film. Furthermore, in some cases, disconnection may occur in the wiring.

前述した問題を生じないように凹凸のある前記絶縁膜表
面を平坦化し、前記絶縁膜に物理的なストレスが発生し
ないようにすることが行なわれている。前記平坦化の方
法としては、レジストエツチングバック法、バアイスス
パッタ法が主に行なわれている。しかしながら、前者は
半導体素子の微細化が進行するにつれて、プロセスの制
御が困難となっており、後者では素子に損傷を与えてし
まうという欠点がある。
In order to avoid the above-described problem, the uneven surface of the insulating film is flattened to prevent physical stress from occurring in the insulating film. As the flattening method, resist etching back method and bias sputtering method are mainly used. However, the former method has become difficult to control as semiconductor devices become smaller and smaller, and the latter method has the drawback of damaging the device.

そこで、上記2つの方法とは別の方法として液体の流動
性を用いた塗布法により、前記段差を平坦化する方法が
有力となってきた。
Therefore, as a method different from the above two methods, a method of flattening the step by a coating method using fluidity of a liquid has become popular.

前記塗布法により形成される塗布膜は配線や半導体素子
を絶縁膜で被覆した後、前記絶縁膜状に硅素化合物を溶
媒中に溶解させた塗布膜形成溶液等を回転塗布し、その
後熱処理により溶媒を揮発させた上、膜の硬化を行なっ
て形成している。
The coating film formed by the above-mentioned coating method is obtained by coating wiring and semiconductor elements with an insulating film, then spin-coating a coating film-forming solution in which a silicon compound is dissolved in a solvent onto the insulating film, and then removing the solvent by heat treatment. The film is formed by volatilizing it and then curing the film.

しかしながら、前記熱処理は半導体素子等への影響を考
えると高温で行なうことはできず溶媒は、充分には揮発
していない。そのため塗布膜中に含まれる水分がエツチ
ングプロセスで使用されたノ10ゲンガスの残留元素等
と反応して配線あるいは半導体素子を腐食させる等、耐
湿性に問題がある。
However, the heat treatment cannot be carried out at high temperatures in view of the effects on semiconductor elements and the like, and the solvent is not sufficiently volatilized. Therefore, there are problems with moisture resistance, such as the moisture contained in the coating film reacting with residual elements of the gas used in the etching process and corroding the wiring or semiconductor elements.

このため、単独で層間絶縁膜として用いず、例えばブラ
ダCVD1ffl膜/塗布膜/プラズマCVD絶縁膜等
塗布膜を他の絶縁膜で挟み込むta層構造しかしながら
基板上の配線層等゛と、絶縁膜及び塗布膜の熱膨張係数
(α)はそれぞれ異なり、特ニ前記配線層がアルミニウ
ム合金で、絶縁膜がプラズマCvDによるSiO2膜の
場合、αは2ケタ異なる。従って、積層構造の層間絶縁
膜を形成しても塗布膜の硬化のための熱処理時に配線層
と絶縁膜の間で熱応力が発生し、前記絶縁膜にクラック
化じる場合があり問題となっている。
For this reason, the TA layer structure is not used alone as an interlayer insulating film, but rather has a TA layer structure in which a coated film such as a bladder CVD 1ffl film/coated film/plasma CVD insulating film is sandwiched between other insulating films. The thermal expansion coefficients (α) of the coated films are different, and in particular, when the wiring layer is an aluminum alloy and the insulating film is an SiO2 film formed by plasma CVD, the coefficients of thermal expansion (α) differ by two digits. Therefore, even if an interlayer insulating film with a laminated structure is formed, thermal stress is generated between the wiring layer and the insulating film during heat treatment to harden the coating film, which may cause cracks in the insulating film, which poses a problem. ing.

(発明が解決しようとする課題) 本発明は上記した従来の配線あるいは半導体素子を絶縁
膜で被覆する方法では、前記絶縁膜の凹凸を平坦化し、
かつ、前記絶縁膜へのクラックの発生が生じてしまうと
いう問題を鑑みてなされたものである。すなわち、本発
明は配線層等の段差部を被覆する絶縁膜とこの絶縁膜上
に形成される塗布膜を低温で形成し、前記絶縁膜へのク
ラックの発生が生じないようにする半導体装置の製造方
法を提供することを目的とする。
(Problems to be Solved by the Invention) The present invention provides that, in the above-described conventional method of covering wiring or semiconductor elements with an insulating film, the unevenness of the insulating film is flattened,
Moreover, this was done in view of the problem that cracks may occur in the insulating film. That is, the present invention provides a semiconductor device in which an insulating film covering a stepped portion such as a wiring layer and a coating film formed on this insulating film are formed at a low temperature to prevent cracks from occurring in the insulating film. The purpose is to provide a manufacturing method.

[発明の構成] (課題を解決するための手段) 本発明は上記目的を達成するために表面に段差部を有す
る基板上に少なくとも前記段差部を被覆する絶縁層を形
成する工程と、前記絶縁層を酸素、窒素、あるいはO族
元素のいずれかを含むガスプラズマ中にさらす工程とを
含む半導体装置の製造方法を提供する。
[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a step of forming an insulating layer covering at least the stepped portion on a substrate having a stepped portion on the surface; A method of manufacturing a semiconductor device is provided, which includes a step of exposing a layer to a gas plasma containing oxygen, nitrogen, or an O group element.

(作用) 本発明により段差部を被覆した絶縁層をプラズマ中にさ
らすことにより低温で前記絶縁膜表面を平坦化すること
ができ、前記絶縁膜にクラックを発生することはない。
(Function) According to the present invention, by exposing the insulating layer covering the stepped portion to plasma, the surface of the insulating film can be flattened at a low temperature, and no cracks will occur in the insulating film.

また、塗布膜の硬化処理は低温におけるプラズマ中で反
応が促進せしめることができ、耐湿性を向上せしめるこ
とが可能である。
In addition, the hardening treatment of the coating film can accelerate the reaction in plasma at low temperatures, making it possible to improve moisture resistance.

例えば、前記塗布膜がSi(OH)4等の硅素化合物の
場合、5i−OH−0H−8tの間で脱水縮合反応を起
こし、5t−0−3iの網目を広げることにより前記塗
布膜の効果が進行するとともに耐湿性を向上せしめるこ
とができる。この場合の処理温度は、熱処理により効果
を行なうには400℃以上の加熱が必要である)この場
合絶縁膜にはクラックが生じる)のに対し、前記クラッ
クを生じることなく400℃以下の低温で行なうことが
できる。また、配線にも応力が加わらないので断線が生
じることはない。
For example, when the coating film is a silicon compound such as Si(OH)4, a dehydration condensation reaction occurs between 5i-OH-0H-8t, and the 5t-0-3i network is widened to increase the effectiveness of the coating film. As this progresses, moisture resistance can be improved. In this case, the processing temperature is 400°C or higher for the heat treatment to be effective (in this case, cracks occur in the insulating film); can be done. Further, since stress is not applied to the wiring, there is no possibility of disconnection.

これは、プラズマ中に前記塗布膜をさらすと、S i 
−OHあるいはO−H結合がプラズマのエネルギーによ
り活性化され反応性に富むからである。
This means that when the coating film is exposed to plasma, Si
This is because -OH or O-H bonds are activated by plasma energy and are highly reactive.

従って、本発明によれば低温で平坦性、耐湿性の良好な
塗布膜を形成することができる。また、これにより、絶
縁層へのクラックの発生あるいは配線層の断線等を生じ
ることはない。
Therefore, according to the present invention, a coating film with good flatness and moisture resistance can be formed at low temperatures. Moreover, this prevents cracks from occurring in the insulating layer or disconnection from the wiring layer.

(実施例) 以下、本発明の一実施例について図面を用いて詳細に説
明する。第1図は、その工程断面図である。
(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a sectional view of the process.

先ず、第1図(a)に示すように例えば第n番目のアル
ミニウム等の配線(1)が形成された基板(6)ニ第1
プラズvcVD−8LO2膜(2)ヲ形成する。次に第
1図(b)に示す様に、前記・プラズマCVD−8i0
2膜(2)の形成された基板全面にシリケート系化合物
を含む塗布膜形成溶液を塗布し、その後、減圧下で塗布
膜形成溶液の溶媒を揮発させ塗布膜としてシリケート系
化合物幕(3)を基板上に残す。ここで、前記塗布膜形
成溶液は硅素化合物を溶媒中に分散あるいは溶解させた
ものを用いることができる。引続き第1図(C)に示す
様に酸素プラズマ中で硬化処理を施したシリケート系化
合物膜(3a)を形成する。ここで、シリケート系化合
物膜(3a)を形成した後、エツチングして全面により
平坦性をもたせるようにしてもよい。
First, as shown in FIG. 1(a), the first
A plasma vcVD-8LO2 film (2) is formed. Next, as shown in FIG. 1(b), the plasma CVD-8i0
2. A coating film forming solution containing a silicate compound is applied to the entire surface of the substrate on which the film (2) is formed, and then the solvent of the coating film forming solution is evaporated under reduced pressure to form a silicate compound curtain (3) as a coating film. Leave it on the board. Here, as the coating film forming solution, a solution in which a silicon compound is dispersed or dissolved in a solvent can be used. Subsequently, as shown in FIG. 1(C), a silicate compound film (3a) which has been hardened in oxygen plasma is formed. Here, after the silicate compound film (3a) is formed, it may be etched to make the entire surface more flat.

また、この実施例では、シリケート系化合物膜(3)を
すべて硬化した例を示したが、前記シリケート系化合物
膜(3)等の塗布膜表面のみを硬化せしめるようにして
も効果が得られる。
Furthermore, although this example shows an example in which the silicate compound film (3) is entirely cured, the effect can also be obtained by curing only the surface of the coating film such as the silicate compound film (3).

この場合、基板温度300”C1酸素圧力I Torr
In this case, the substrate temperature is 300"C1, the oxygen pressure is I Torr
.

Rp’ ハワーsoow、処理時間30分のプラズマ処
理により、前記塗布膜はその表面がら深さ方向に約20
00A迄ち密化することができた。特に凸部上での塗布
膜膜厚は〜500A程度であ−るので、前記凸部上の塗
布膜は極めて良好に改質されていた。
By plasma treatment for 30 minutes, the coating film has a depth of about 20 mm from its surface.
We were able to maintain tightness until 00A. In particular, since the thickness of the coating film on the protrusions was about 500 Å, the coating film on the protrusions was extremely well modified.

さらに第1図(d)に示す様に第2プラズマcvD−8
i02膜(4)を層間絶縁膜として形成し、さらにその
上に第1図(e)に示す様な第(n+1)アルミニウム
配線(5)を形成する。
Furthermore, as shown in FIG. 1(d), the second plasma CVD-8
An i02 film (4) is formed as an interlayer insulating film, and an (n+1)th aluminum wiring (5) as shown in FIG. 1(e) is further formed thereon.

上記実施例で形成した第n番目のアルミニウム配線(1
)がアルミニウム幅2μ謀、スペース幅2μ■、アルミ
ニウム厚1μ電のラインアンドスペースパターンであり
、′!B1プラズマCVD−3i02膜(2)ノ膜厚0
.2μs+7)条件で450℃の熱処理により塗布膜(
3)を硬化させた場合、第1プラズマCVD−5i02
膜(2)に生じるクラックの発生率は30%であった。
The n-th aluminum wiring (1
) is a line and space pattern with an aluminum width of 2μ, a space width of 2μ■, and an aluminum thickness of 1μ, and '! B1 plasma CVD-3i02 film (2) film thickness 0
.. The coating film (
3), the first plasma CVD-5i02
The incidence of cracks in film (2) was 30%.

その後、さらに基板温度を室温〜300℃、酸素圧力I
 TorrSRFパワー800W、処理時間60分の酸
素ブロズマ処理により塗布膜(3)を硬化させた場合、
CVD−3i02膜(2)にクラックは全く発生しない
After that, the substrate temperature was further increased from room temperature to 300°C, and the oxygen pressure was
When the coating film (3) is cured by oxygen brosma treatment with TorrSRF power of 800W and treatment time of 60 minutes,
No cracks occur in the CVD-3i02 film (2).

本発明により形成する塗布膜の膜質は、第1あるいは第
2の絶縁膜との間で発生する応力の影響を抑制するため
に膜質を極力近付けるのが望ましい。
It is desirable that the film quality of the coating film formed according to the present invention be as close as possible to the first or second insulating film in order to suppress the influence of stress generated between the coating film and the first or second insulating film.

前記膜質の比較のため両者のエツチング速度を調べた結
果について以下説明する。
In order to compare the film quality, the etching rates of both films were investigated and the results will be explained below.

第2図は塗布膜の硬化処理を施す際に基板温度を変化さ
せた時の塗布膜((^)熱処理、(B)プラズマ処理)
とプラズマCVD−8io2膜(C) ノエッチング速
度を示す特性図である。
Figure 2 shows the coating film when the substrate temperature is changed during the hardening treatment of the coating film ((^) heat treatment, (B) plasma treatment)
and plasma CVD-8io2 film (C).

ここでプラズマ処理は酸素(o2)雰囲気中で行ない、
酸素圧力I Torr、RF出カ800Wll!L理時
間60分の処理条件である。また、プラズマCVp−S
i02膜のエツチング速度は基板温度によらずエツチン
グ速度はほぼ一定であり、基板温度が300℃前後のと
きに両者のエツチング速度がほぼ同様であることがゎが
った。
Here, the plasma treatment is performed in an oxygen (O2) atmosphere,
Oxygen pressure I Torr, RF output 800Wll! The processing conditions were 60 minutes. In addition, plasma CVp-S
The etching rate of the i02 film was almost constant regardless of the substrate temperature, and it was found that when the substrate temperature was around 300°C, the etching rates of both were almost the same.

さらに塗布膜の硬化処理後のエツチング速度を熱処理で
行った場合(、A)と本発明によるプラズマ処理で行っ
た場合(B)で比較すると、例えば、プラズマ処理の3
00”Cのエツチング速度は、熱処理を600℃〜で行
った場合とほぼ同様、であった。
Furthermore, when comparing the etching speed after hardening of the coating film when heat treatment is performed (A) and when plasma treatment according to the present invention is performed (B), for example,
The etching rate at 00''C was almost the same as when the heat treatment was performed at 600°C or higher.

これらのことから、プラズマ処理により硬化させた塗布
膜の方が熱処理により硬化させたよりもプラズマCVD
−8i02膜の膜質に近いことが推察される。
For these reasons, coating films cured by plasma treatment are better than those cured by heat treatment by plasma CVD.
It is inferred that the film quality is close to that of the -8i02 film.

また、第2図から、プラズマ処理を施した塗布膜は同一
基板温度における通常の熱処理に比べた場合よりエツチ
ング速度が遅く、膜が緻密であることがわかる。従って
、同一基板温度では、熱処理よりもプラズマ処理の方が
吸湿性が小さいことがわかる。
Furthermore, from FIG. 2, it can be seen that the etching rate of the coating film subjected to plasma treatment is slower than that of the case of ordinary heat treatment at the same substrate temperature, and the film is denser. Therefore, it can be seen that, at the same substrate temperature, plasma treatment has lower hygroscopicity than heat treatment.

このことは、塗布膜を沸騰水中に約30分浸した後、塗
布膜を加熱した時に放出される水の相対量を質量分析計
を用いて測定することにより明らかとなった。
This became clear by using a mass spectrometer to measure the relative amount of water released when the coating film was heated after immersing the coating film in boiling water for about 30 minutes.

すなわち、基板温度300℃、酸素圧力I Torrs
RF、800W、処理時間60分の条件で形成された塗
布膜はプラズマCVD−5i02膜と同程度であり、熱
処理により硬化せしめた膜に比べ吸湿性は約1/10と
大きく改善された。
That is, the substrate temperature is 300°C and the oxygen pressure is I Torrs.
The coating film formed under the conditions of RF, 800 W, and 60 minutes of processing time was comparable to the plasma CVD-5i02 film, and its hygroscopicity was significantly improved to about 1/10 compared to the film cured by heat treatment.

なお、上記実施例では塗布膜を酸素プラズマにさらした
が、酸素、窒素、あるいはアルゴン、ヘリウム、ネオン
等の0族元素を含むガスプラズマにさらしても同様の効
果が得られる。また、塗布膜形成溶液はプラズマにさら
した時に硬化する材料であれば何でもよいが、望ましく
は、シリコン(SL)と酸素(0)を含むものがよい。
In the above embodiments, the coating film was exposed to oxygen plasma, but the same effect can be obtained by exposing it to oxygen, nitrogen, or gas plasma containing Group 0 elements such as argon, helium, and neon. Further, the coating film forming solution may be any material as long as it hardens when exposed to plasma, but preferably one containing silicon (SL) and oxygen (0).

また、前記塗布膜をプラズマにさらす直前あるいはプラ
ズマにさらしている間に基板に熱処理を加えると硬化処
理の時間を短縮でき、スループットを向上させることが
できる。
Further, if the substrate is subjected to heat treatment immediately before or while the coating film is exposed to plasma, the time for curing treatment can be shortened and throughput can be improved.

さらに、上記実施例では塗布膜として、シリケート系化
合物膜が表面に形成された絶縁膜の例を示したが、本発
明ではテトラエトキシシラン(TEOS)等の有機硅素
化合物を原料として化学的気相成長法による薄膜を形成
し、5i−R(アルキル基)、5t−OR(アルコキシ
基)等の有機基がその膜中に存在する絶縁膜を改質する
場合も含む。例えば、TEOSを原料としてプラズマC
VD法で、層間絶縁膜として用いるために基板温度が〜
400℃の低温で膜の堆積を行った場合、膜中にエトキ
シ基と副反応生成物の有機基が残る。この場合、膜堆積
とプラズマ処理による膜の改質とを交互に行う。有機基
を完全に除きながら所定膜厚になるまで膜堆積とプラズ
マ処理による膜の改質とを繰返すことにより膜中に有機
基のないち密な膜を形成することが、上記実施例と同様
にできる。
Further, in the above embodiment, an example of an insulating film having a silicate compound film formed on the surface was used as the coating film, but in the present invention, a chemical vapor phase coating using an organosilicon compound such as tetraethoxysilane (TEOS) as a raw material is used. It also includes a case where a thin film is formed by a growth method and an insulating film in which organic groups such as 5i-R (alkyl group) and 5t-OR (alkoxy group) are present is modified. For example, using TEOS as a raw material, plasma C
In the VD method, the substrate temperature increases to ~
When a film is deposited at a low temperature of 400° C., ethoxy groups and organic groups as side reaction products remain in the film. In this case, film deposition and film modification by plasma treatment are performed alternately. As in the above example, it is possible to form a dense film with no organic groups in the film by repeating film deposition and modification of the film by plasma treatment until a predetermined film thickness is achieved while completely removing organic groups. can.

また、上記実施例では、表面に段差部を有する基板とし
て配線パターンが基板上に形成されたものについて示し
たが、その他、段差部のある領域であれば、半導体素子
の形成された領域等にも応用することができる。
Further, in the above embodiment, a wiring pattern is formed on the substrate as a substrate having a stepped portion on the surface. can also be applied.

【発明の効果] 以上述べたように本発明によれば基板の配線等の段差部
を被覆した絶縁層の表面を低温で平坦化することができ
、プロセスにおける絶縁層あるいは、配線への影響を抑
制することができる。
[Effects of the Invention] As described above, according to the present invention, it is possible to flatten the surface of the insulating layer covering the stepped portion of the wiring of the substrate at a low temperature, thereby reducing the influence on the insulating layer or the wiring during the process. Can be suppressed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による一実施例を示す工程断面図、第2
図は本発明の詳細な説明するための特性図である。 1.5・・・配線、   2・・・第1の絶縁層、3・
・・塗布膜、    4・・・第2の絶縁層、6・・・
基板。
Fig. 1 is a process sectional view showing one embodiment of the present invention;
The figure is a characteristic diagram for explaining the present invention in detail. 1.5... Wiring, 2... First insulating layer, 3...
... Coating film, 4... Second insulating layer, 6...
substrate.

Claims (3)

【特許請求の範囲】[Claims] (1)表面に段差部を有する基板上に少なくとも前記段
差部を被覆する絶縁層を形成する工程と、前記絶縁層を
酸素、窒素、あるいはO族元素のいずれかを含むガスプ
ラズマ中にさらす工程とを含む半導体装置の製造方法。
(1) A step of forming an insulating layer covering at least the step portion on a substrate having a step portion on the surface, and a step of exposing the insulating layer to a gas plasma containing oxygen, nitrogen, or an O group element. A method for manufacturing a semiconductor device, including:
(2)表面に段差部を有する基板上に少なくとも前記段
差部を被覆する第1の絶縁層を形成する工程と、前記第
1の絶縁層上に塗布膜を形成し、前記第1の絶縁膜の形
成された基板表面を平坦化する工程、と、その後、少な
くとも前記塗布膜をプラズマ中にさらす工程と、前記平
坦化された塗布膜上に第2の絶縁層を形成する工程とを
含む請求項1記載の半導体装置の製造方法。
(2) forming a first insulating layer covering at least the step portion on a substrate having a step portion on the surface; forming a coating film on the first insulating layer; and forming a coating film on the first insulating layer; A claim comprising the steps of: planarizing the surface of the substrate on which is formed; thereafter, exposing at least the coating film to plasma; and forming a second insulating layer on the planarized coating film. Item 1. A method for manufacturing a semiconductor device according to item 1.
(3)表面に段差部を有する基板上に気相中のガス分解
により少なくとも前記段差部を被覆する絶縁層を形成す
る工程と、少なくとも前記絶縁膜表面プラズマ中にさら
す工程とを含む請求項1記載の半導体装置の製造方法。
(3) A step of forming an insulating layer covering at least the step portion on a substrate having a step portion on the surface by gas decomposition in a gas phase, and a step of exposing at least the surface of the insulating film to plasma. A method of manufacturing the semiconductor device described above.
JP63003241A 1988-01-12 1988-01-12 Method for manufacturing semiconductor device Expired - Lifetime JP2883333B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63003241A JP2883333B2 (en) 1988-01-12 1988-01-12 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63003241A JP2883333B2 (en) 1988-01-12 1988-01-12 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH01181533A true JPH01181533A (en) 1989-07-19
JP2883333B2 JP2883333B2 (en) 1999-04-19

Family

ID=11551960

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2883333B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002009151A (en) * 2000-06-21 2002-01-11 Seiko Epson Corp Semiconductor device and its manufacturing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154029A (en) * 1983-02-23 1984-09-03 Nippon Telegr & Teleph Corp <Ntt> Formation of insulating film
JPS6163020A (en) * 1984-09-04 1986-04-01 Agency Of Ind Science & Technol Formation of thin film
JPS6265427A (en) * 1985-09-18 1987-03-24 Nec Corp Flattening method
JPS6266635A (en) * 1985-09-19 1987-03-26 Nec Corp Flattening method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154029A (en) * 1983-02-23 1984-09-03 Nippon Telegr & Teleph Corp <Ntt> Formation of insulating film
JPS6163020A (en) * 1984-09-04 1986-04-01 Agency Of Ind Science & Technol Formation of thin film
JPS6265427A (en) * 1985-09-18 1987-03-24 Nec Corp Flattening method
JPS6266635A (en) * 1985-09-19 1987-03-26 Nec Corp Flattening method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002009151A (en) * 2000-06-21 2002-01-11 Seiko Epson Corp Semiconductor device and its manufacturing method
JP4585656B2 (en) * 2000-06-21 2010-11-24 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
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