JPS6266635A - Flattening method - Google Patents

Flattening method

Info

Publication number
JPS6266635A
JPS6266635A JP20841885A JP20841885A JPS6266635A JP S6266635 A JPS6266635 A JP S6266635A JP 20841885 A JP20841885 A JP 20841885A JP 20841885 A JP20841885 A JP 20841885A JP S6266635 A JPS6266635 A JP S6266635A
Authority
JP
Japan
Prior art keywords
film
resin
polymer
sio2
siloxane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20841885A
Other languages
Japanese (ja)
Inventor
Ichiro Moriyama
森山 一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20841885A priority Critical patent/JPS6266635A/en
Publication of JPS6266635A publication Critical patent/JPS6266635A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain a flat insulating film on a step by coating it with resin which mainly contains siloxane polymer to flatten a certain surface of the step, oxidizing the upper layer to modify it to an SiO2 film, selectively removing it and then oxidizing the remaining resin film as SiO2 film. CONSTITUTION:A substrate 1 having a step of approx. 0.5mum is rotatably coated with siloxane polymer to form a resin film 5 of approx. 1mum thick, and the film is treated at 200 deg.C in N2. When using a polymer having CH3 group and OH group as substituted groups and a 3-dimensional structure, the polymer can be coated in large thickness, and a crack hardly occurs at contraction time. An upper layer film 6 is converted to SiO2 to 0.3mum thick of the film 5 from the projection of the substrate 1. Only the film 6 is selectively removed with aqueous HF solution, the remaining film 5 is completely converted to SiO2 by plasma oxidizing to modify it to an insulating film 6. This flattening method has less crack, simple steps, and ready process controllability to be utilized for various processes.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造工程において、段差を表面
に有する半導体基板の表面を平坦化する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for planarizing the surface of a semiconductor substrate having a step on the surface in a semiconductor device manufacturing process.

〔従来の技術〕[Conventional technology]

従来、大規模集積回路(LSI)の製造工程において、
多層配線の層間絶縁膜や積層形半導体装置の層間絶縁膜
の表面を平坦化するには、リンガラスフロー、樹脂絶縁
法、樹脂塗布及びエツチングなど様々な方法が用いられ
ている。例えば、第1回次世代産業基盤技術シンdジク
ム、昭和58年7月の192ページから195ページ掲
載の高浜開音による文献1■平坦化技術#においては、
スピンオンガラス全周いた塗布及びエツチングによる平
坦化方法が報告されている。
Conventionally, in the manufacturing process of large-scale integrated circuits (LSI),
To planarize the surface of the interlayer insulating film of multilayer wiring or the interlayer insulating film of a stacked semiconductor device, various methods such as phosphor glass flow, resin insulation method, resin coating, and etching are used. For example, in Document 1 Flattening Technology # by Kaion Takahama published in the 1st Next Generation Industrial Basic Technology Synd, July 1988, pages 192 to 195,
A method of flattening spin-on glass by coating and etching the entire circumference has been reported.

この平坦化方法で用いるスピンオンがラストハシラノー
ル(81(OH)4) k主成分とする溶液であシ、半
導体基板にスピン途布し次いで熱処理によシこれを固化
することによってSlO□膜を形成するものである。以
下、第2図(a)、(b)シC)に示した模式的断面図
によシこの平坦化方法の基本的工程を説明する。
The spin-on used in this planarization method is a solution mainly composed of last-hasilanol (81(OH)4), which is spun onto a semiconductor substrate and then solidified by heat treatment to form a SlO It is something that forms. The basic steps of this planarization method will be explained below with reference to the schematic cross-sectional views shown in FIGS. 2(a) and 2(b) (C).

図中、1は下地基板、2 it CVD 810211
に、 3は塗布直後のスピンオンがラス膜、4は5tO
2化したスピンオンガラス膜である。まず、第2図(、
)に示すように、段差を有する下地基板1上に眉間絶縁
膜に対応するSIO□膜2’1CVD法によシ形成し、
次いでスピンオンガラスをスピン塗布法によシ塗布し段
差を塗布[3で埋めて表面を平坦化する0次に、第2図
(b)に示すように、窒素雰囲気で800℃1時間の熱
処理によシスピンオンがラス塗布膜3を固化し810□
化した塗布膜4に変質させる。この時、スピンオンガラ
ス塗布膜3の縮合反応により塗布膜4の膜厚が減少する
。最後に、第2図(、)に示すように、8102化した
塗布膜4と下地CVD 810. JIBとを等エツチ
ング速度で必要な厚さまでエツチングする。
In the figure, 1 is the base substrate, 2 it CVD 810211
In 3, the spin-on is a lath film immediately after coating, and in 4, 5tO
This is a divisible spin-on glass film. First, Figure 2 (,
), an SIO□ film 2'1 corresponding to the glabellar insulating film is formed on the base substrate 1 having a step by the CVD method,
Next, spin-on glass was applied using a spin coating method to fill in the steps to flatten the surface.Next, as shown in Figure 2(b), heat treatment was performed at 800°C for 1 hour in a nitrogen atmosphere. Yosis pin-on solidifies the lath coating film 3 and 810□
The coating film 4 is changed in quality. At this time, the thickness of the coating film 4 decreases due to the condensation reaction of the spin-on glass coating film 3. Finally, as shown in FIG. JIB is etched at the same etching speed to the required thickness.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記平坦化方法は、スピンオンガラスがスピン塗布によ
シ表面の平坦化が可能であるような液状の材料であるこ
と、また熱処理によって810□化することから不純物
の汚染による悪影響もなくStO,化したスピンオンガ
ラスによる塗布膜4をそのまま残すことも可能であるな
どの利点をもっている。しかし、一方スビンオンガラス
塗布膜のStO□化の反応は基本的に下記のようなシラ
ノールモノマーの縮合反応によるものであシ、体積の収
縮率が大きくクラックが発生しやすい欠点をもっている
The flattening method described above is possible because spin-on glass is a liquid material that can flatten the surface by spin coating, and because it is converted to 810□ by heat treatment, there is no adverse effect due to impurity contamination, and it is not converted into StO. It has the advantage that it is possible to leave the coated film 4 made of spin-on glass as it is. However, on the other hand, the reaction of forming the StO□ coating film on glass is basically based on the condensation reaction of silanol monomers as described below, and has the disadvantage of a high volume shrinkage rate and a tendency to generate cracks.

また、上記のようにスピンオンガラス膜はシラノールモ
ノマーが主成分であるため厚く塗布することが困難であ
シ、例えば約1μ−の段差を平坦化するKは、4〜5回
糧度重ね塗布する必要がある。
In addition, as mentioned above, since the spin-on glass film is mainly composed of silanol monomer, it is difficult to apply it thickly.For example, K, which flattens a level difference of approximately 1μ, is coated 4 to 5 times. There is a need.

さらに、StO□化したシラノール系塗布膜と下地CV
D 8102膜を等エツチング速度で必要な厚さまで制
御よくエツチングすることは非常に離しい。このように
、上記平坦化方法によればクラックの発生など信頼性に
問題があシかつ工程数が多くプロセス制御が難しいこと
から、LSIの調造方法として用いるには困難であると
考えられていた。
Furthermore, the StO□ silanol coating film and the base CV
It is very difficult to controllably etch D8102 films to the required thickness at uniform etch rates. As described above, the above-mentioned planarization method has problems with reliability such as the occurrence of cracks, and requires a large number of steps and is difficult to control, so it is considered difficult to use as a method for preparing LSIs. Ta.

本発明の目的は上記の問題点を解決した平坦化方法を提
供することにある。
An object of the present invention is to provide a planarization method that solves the above problems.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は段差を有する半導体基板の表面を平坦1   
化する方法において、該基板上にシロキサン系I□ 1   リマーを主成分とする樹脂を塗布することによ
シ表面を平坦化し1次いで上記樹脂膜の上層部を酸化し
てStO□釦変質させ、との5tO2化した上層部のみ
を選択的にエツチング除去し、残存した樹脂膜を酸化し
810□に変質させることによって上記半導体基板上に
形成された段差上に平坦な絶縁膜を形成するものである
The present invention flattens the surface of a semiconductor substrate having steps.
In this method, the surface is flattened by coating the substrate with a resin containing siloxane-based I□1 reamer as a main component, and then the upper layer of the resin film is oxidized to change the quality of the StO□ button. This method forms a flat insulating film on the step formed on the semiconductor substrate by selectively etching away only the upper layer that has been converted to 5tO2 and oxidizing the remaining resin film to change its quality to 810□. be.

本発明の平坦化方法の重要な点は段差を有する半導体基
板の表面を平坦化する塗布材料にシロキサン系ポリマー
を主成分とする樹脂を用いた点であシ、この樹脂は酸化
することによシ810□化されることを利用したもので
ある。
An important point of the planarization method of the present invention is that a resin containing a siloxane-based polymer as a main component is used as a coating material for planarizing the surface of a semiconductor substrate having steps, and this resin does not oxidize. This takes advantage of the fact that the image is converted into 810□.

ここで、上記樹脂の酸化によるStO□化は酸素雰囲気
中の熱処理iたは酸素プラズマ酸化またはオゾン雰囲気
中の熱処理いずれKよりてもよい。
Here, the conversion of the resin into StO□ by oxidation may be performed by heat treatment in an oxygen atmosphere, oxygen plasma oxidation, or heat treatment in an ozone atmosphere.

〔作用〕[Effect]

シロキサン系/ IJママ−基本的に下記の(A)のよ
うな2次元的ポリマーあるいは(B)のような3次元ポ
リマーを形成している。
Siloxane-based/IJ mom-Basically, it forms a two-dimensional polymer as shown in (A) below or a three-dimensional polymer as shown in (B).

RR (A)          (B) ここで、RはH、OH、CM、 # C2H5,フェニ
ル基等の置換基に対応している。このようなポリマー構
造はシラノールなどのモノマーに対して厚く塗布するこ
とが可能である。また、塗布後の熱処理による収縮率も
置換基を選択することによシ低減させることができる。
RR (A) (B) Here, R corresponds to a substituent such as H, OH, CM, #C2H5, or a phenyl group. Such polymer structures can be coated thickly with monomers such as silanols. Furthermore, the shrinkage rate due to heat treatment after coating can be reduced by selecting substituents.

また、このようなシロキサン系ポリマーは酸素雰囲気中
での熱処理や酸素プラズマ酸化やオゾン雰囲気中の熱処
理によって酸化しStO,化する。このとき酸化反応は
シロキサン系ポリマー膜の上層部から進行するため、酸
化条件によって5tO2化した膜厚を制御することが可
能でおる。さらに、シロキサン系ポリマーはフッ酸系溶
液によシはとんどエツチングされないのに対し810□
化したシロキサン系ポリマーのエツチング速度は大きい
。従って、塗布したシロキサン系ポリマー膜を必要な膜
厚のシロキサン系ポリマー膜が残るように上層部のみS
iO2化し、そのStO□化したシロキサン系、74リ
マー膜のみを7ツ酸系エツチング溶液で選択的にエツチ
ング除去し、最後に残りたシロキサン系ポリマー膜を完
全にStO□化することが可能である。
Moreover, such a siloxane-based polymer is oxidized to StO by heat treatment in an oxygen atmosphere, oxygen plasma oxidation, or heat treatment in an ozone atmosphere. At this time, since the oxidation reaction proceeds from the upper layer of the siloxane polymer film, it is possible to control the thickness of the 5tO2 film by adjusting the oxidation conditions. Furthermore, siloxane-based polymers are hardly etched by hydrofluoric acid-based solutions, whereas 810□
The etching rate of the siloxane-based polymer is high. Therefore, only the upper layer of the applied siloxane-based polymer film is S
It is possible to selectively remove only the siloxane-based 74 remer film that has been converted into iO2 and converted into StO□ with a 7-acid-based etching solution, and finally the remaining siloxane-based polymer film can be completely converted into StO□. .

〔実施例〕〔Example〕

以下、第1図(鳳)−(b)−(c)、(d)の模式的
断面図忙よシ本発明による平坦化方法の実施例を説明す
る。
Hereinafter, an embodiment of the planarization method according to the present invention will be described based on the schematic cross-sectional views of FIGS. 1-(b)-(c) and (d).

図中、1は第2図の1と同じ下地基板でおシ、5はシロ
キサン系ポリマーを主成分とする樹脂膜、6はSiO2
化したシロキサン系ポリマーを主成分とする樹脂膜であ
る。tず、第1図(1)に示すように、0.5μmの段
差を表面に有する下地基板l上にシロキサン系ポリマー
をスピン塗布法によ91.0μm塗布して樹脂膜5を形
成し、窒素雰囲気中で200℃1時間熱処理した。ここ
で、シロキサン系ポリマーとしては置換基K CM、基
及びOH基をもち、かつ3次元的な構造をもつぼりマー
を用いた。このシロキサン系ポリマーは一度に厚く塗布
することが可能であシ、また縮合反応における収縮率も
小さいのでクラックが発生しにくい。次に、第1図(b
)に示すよう忙、02ガスによるグラズマ酸化によシ下
地基板lの凸部から樹脂[5の厚さが0.3μmになる
まで上層部の樹脂膜6’t−酸化してStO□化した樹
脂1[6に変質させた。この時のプラズマ酸化条件は、
円筒匿グラズマ発生装置を用い、0□がス流量20 s
ecm 、Wス圧力1.2Torr s高周波電力20
0Wである0次に、第1図(e) Ilc示すようK、
7ツ酸水溶液(IF : H2O−1: 30 )Il
cよシ上層部の5io2化した樹脂膜6のみを選択的に
エツチング除去した。最後に、第1図(d)k示すよう
に残存した樹脂膜5を前記プラズマ酸化条件で完全IC
810□化して樹脂[6に変質させる。このよう忙して
、段差上に0.3μmの厚さKなるように平坦化した絶
縁膜、すなわちS tO2化した樹脂膜6を形成するこ
とができた。
In the figure, 1 is the same base substrate as 1 in Figure 2, 5 is a resin film mainly composed of siloxane polymer, and 6 is SiO2.
This is a resin film whose main component is a siloxane-based polymer. First, as shown in FIG. 1 (1), a resin film 5 was formed by applying a 91.0 μm thick siloxane-based polymer on a base substrate l having a step of 0.5 μm on the surface by a spin coating method. Heat treatment was performed at 200° C. for 1 hour in a nitrogen atmosphere. Here, as the siloxane polymer, a streamer having a substituent K CM group and an OH group and having a three-dimensional structure was used. This siloxane-based polymer can be applied thickly at one time, and has a small shrinkage rate during the condensation reaction, so cracks are less likely to occur. Next, Figure 1 (b
), the upper resin film 6't-oxidized to StO Resin 1 [changed to 6]. The plasma oxidation conditions at this time are:
Using a cylindrical concealed glazma generator, 0□ has a gas flow rate of 20 s.
ecm, W pressure 1.2 Torr s High frequency power 20
At 0th order which is 0W, K as shown in Fig. 1(e) Ilc,
7-acid aqueous solution (IF: H2O-1: 30) Il
Only the 5io2 resin film 6 in the upper layer part c was selectively removed by etching. Finally, as shown in FIG. 1(d)k, the remaining resin film 5 is completely oxidized under the plasma oxidation conditions.
810□ and changes into resin [6]. In this way, we were able to form a flattened insulating film, ie, a resin film 6 made of StO2, on the step to a thickness K of 0.3 μm.

以上のように、上記実施例によればスピンオンがラスを
用いた従来の平坦化方法と同じ効果をもち、かつ一度に
厚く塗布できクラックの発生も低減でき平坦化した絶縁
膜の厚さの制御が容易であるなど従来の平坦化方法の問
題点を解決した平坦化方法が得られた。
As described above, according to the above embodiment, spin-on has the same effect as the conventional planarization method using a lath, can be applied thickly at one time, reduces the occurrence of cracks, and can control the thickness of the planarized insulating film. A planarization method has been obtained that solves the problems of conventional planarization methods, such as easy flattening.

尚、本実施例では塗布する樹脂としてCH,基とOH基
を置換基とする3次元的構造のシロキサン系ポリマーを
主成分とする樹脂を用いたが他のシロキサン系ポリマー
を主成分とする樹脂でも可能である。また、樹脂のSt
O□化の方法として酸素プラズマ酸化を用いたが他の酸
素雰囲気中の熱処理またはオゾン雰囲気中の熱処理いず
れによっても可能である。
In this example, a resin whose main component is a siloxane-based polymer having a three-dimensional structure with CH, and OH groups as substituents was used as the resin to be applied, but other resins whose main component is a siloxane-based polymer may be used. But it is possible. In addition, the resin St
Oxygen plasma oxidation was used as the method for O□ conversion, but other heat treatment in an oxygen atmosphere or heat treatment in an ozone atmosphere may also be used.

〔発明の効果〕〔Effect of the invention〕

以上のように、本発明によれば従来の平坦化方法に比べ
てクラックの発生が少なく工程が簡単でありプロセス制
御が容易であるなど極めて改善された平坦化方法を実現
できる。
As described above, according to the present invention, it is possible to realize a planarization method that is significantly improved compared to conventional planarization methods, such as less occurrence of cracks, a simpler process, and easier process control.

したがって、発明忙よれば信頼性が高く比較的TATの
短い平坦化方法を提供でき、 LSIの装造工程におい
て平坦化が必要な各種工程に広く利用できる効果を有す
る。
Therefore, the present inventors can provide a planarization method that is highly reliable and has a relatively short TAT, and has the effect that it can be widely used in various processes that require planarization in the LSI assembly process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(aMb)、(e)、(d)は本発1511によ
る平坦化方法の製造工程の一実施例を示した模式的断面
図、第2図(a)、(b)、(e)は従来の平坦化方法
の製造工程を示した模式的断面図である。 l・・・下地基板、5・・・シロキサン系−リマーt−
主成分とする樹脂膜、6・・・StO□化したシロキサ
ン系ポリマーを主成分とする樹脂膜。 特許出願人 日本電気株式会社− <b> 見1図 (α) Cb) 2−−CVD5LOzFI貢 第2図
FIGS. 1(aMb), (e), and (d) are schematic cross-sectional views showing an example of the manufacturing process of the flattening method according to the present invention 1511, and FIGS. 2(a), (b), and (e ) is a schematic cross-sectional view showing the manufacturing process of a conventional planarization method. l... base substrate, 5... siloxane-based remer t-
Resin film mainly composed of 6...Resin film mainly composed of siloxane polymer converted into StO□. Patent applicant NEC Corporation - <b> Figure 1 (α) Cb) 2--CVD5LOzFI Figure 2

Claims (1)

【特許請求の範囲】[Claims] (1)段差を有する半導体基板の表面を平坦化する方法
において、該基板の段差上にシロキサン系ポリマーを主
成分とする樹脂を塗布することにより表面を平坦化し、
次いで上記樹脂膜の上層部を酸化してSiO_2に変質
させ、このSiO_2化した上層部のみを選択的にエッ
チング除去し、残存した樹脂膜を酸化しSiO_2に変
質させることによって上記半導体基板上に形成された段
差上に平坦な絶縁膜を形成することを特徴とする平坦化
方法。
(1) In a method for flattening the surface of a semiconductor substrate having a step, the surface is flattened by applying a resin containing a siloxane-based polymer as a main component onto the step of the substrate,
Next, the upper layer of the resin film is oxidized to transform into SiO_2, and only the upper layer that has been converted to SiO_2 is selectively etched away, and the remaining resin film is oxidized and transformed to SiO_2 to form on the semiconductor substrate. A planarization method characterized by forming a flat insulating film on the stepped step.
JP20841885A 1985-09-19 1985-09-19 Flattening method Pending JPS6266635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20841885A JPS6266635A (en) 1985-09-19 1985-09-19 Flattening method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20841885A JPS6266635A (en) 1985-09-19 1985-09-19 Flattening method

Publications (1)

Publication Number Publication Date
JPS6266635A true JPS6266635A (en) 1987-03-26

Family

ID=16555901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20841885A Pending JPS6266635A (en) 1985-09-19 1985-09-19 Flattening method

Country Status (1)

Country Link
JP (1) JPS6266635A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6445148A (en) * 1987-08-13 1989-02-17 Fuji Xerox Co Ltd Semiconductor device and manufacture thereof
JPH01181533A (en) * 1988-01-12 1989-07-19 Toshiba Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6445148A (en) * 1987-08-13 1989-02-17 Fuji Xerox Co Ltd Semiconductor device and manufacture thereof
JPH01181533A (en) * 1988-01-12 1989-07-19 Toshiba Corp Manufacture of semiconductor device

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