A7 B7 _ 五、發明説明（/ ) 發明領域： _ (請先閱讀背面之注意事項再填寫本頁) 本發明係揭露一種製作積體電路中導電層間介電層的方 法，特別是關於一種消弭旋塗式玻璃（Spin on Glass; SOG) 與介電層間空隙（voids)的方法。 發明背景： 近女，隨著積體電路往更小尺寸與更高積極度的方向發 展，使得積體電路的內連線需求，也由以往簡單的二、三層 結構，發展成爲四層以上的多重金屬內連線（Multilevel Interconnects)製程，使得積體電路中每一層的平整度直接 影響多層堆疊架構製作的難易度，成爲現代半導體製程上的 重要考量因素之一。 經濟部智慧財產局員工消費合作社印製 旋塗式玻璃（SOG)的應用是現在普遍採用的一種金屬 層間介電層（Inter-Metal Dielectrics; IMD)局部性平坦化的 技術。SOG是一種相當簡易的平坦化技術，包含塗佈與固化 兩個製程階段，以旋塗（spin coating)的方式將一種溝填能 力非常好的液態介電村料塗佈於晶片上，因爲塗佈的介電材 料可以隨著溶劑在晶片的表面流動，因此可以很容易的填入 結構凹槽內而達到局部平坦化的目的；接著，再利用熱處理 的方式把旋塗式玻璃內的溶劑加以蒸除，使旋塗式玻璃的密 度增加並固化（curing)爲近似於二氧化矽（Si02)的結構， 晶片表面所呈現的平坦性將較化學氣相沉積法（Chemical Vapor Deposition; CVD)所獲得的結果還來的理想。但由於 旋塗式玻璃本身在應用時會造成微粒：當溶劑揮發時會有剝 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） 4369 6 8 A7 B7 五、發明説明（〉） 離及出氣(out gassing)現象產生，在後續製程中會有吸水狀 況出現，而使介電層的表面產生不平坦。 現在廣爲半導體界所使用的旋塗式玻璃（SOG)，通常 爲了確保旋塗式玻璃的物性與化性而採用三明治式 (sandwich type)的結構，係由兩層化學氣相沉積法 (Chemical Vapor Deposition; CVD)所沉積的8102將旋塗式 玻璃包夾，其中所述CVD-Si02通常是利用具備低溫優點的 電策增強化學氣相沉積法（Plasma Enhance Chemical Vapor Deposition; PECVD)形成。然而，此方法的缺點在於，因 爲金屬導線具有較大的膨脹係數，所以熱脹冷縮的現象會較 明顯，經過旋塗式玻璃的固化熱處理之後，晶片溫度下降， 金屬導線向內縮小的情形會較明顯，而因爲CVD-Si02與金 屬導線間有較強的附著力（adhesion)，所以當金屬導線向內 縮小時CVD-Si02會被金屬導線一起帶向內縮，但CVD-Si02 與SOG-SiO/^的附著力不夠，隨著CVD-Si02K向內縮，導 致CVD-SiCy^SOG-Si02間由金屬導線側面（因爲側邊熱脹 冷縮的效應較明顯）剝離形成空隙（voids)，而產生產品可 靠度(Reliability)與良率(Yield)的問題。 因此，爲解決習知技術中所造成之問題’本發明提供一 種製作積體電路中導電層間介電層的方法’用以消弭複層介 電層間空隙的形成。 發明之概述： 本發明之主要目的是提供一種製作積體電路中導電層間 介電層的方法，利用降低導電層與介舍層間的附著力，避免 本紙張尺度適用中國國家標隼（CMS ) A4規格（21〇X：2i7公釐） 身-- I - - (請先聞讀背面之注意事項再填寫本頁) --β 經濟部智慧財產局員工消費合作杜印製 A7 4369 6 8 五、發明説明（j ) 介電層間空隙的形成，提高產品的可靠度與良率。 本發明係使用下列步驟來達到上述之目的：首先，提供 一已完成前段製程的半導體基板，形成一導電層於所述基板 上；接著，於蝕刻所述導電層時加入一可降低導線結構與介 電層間附著力的氣體；再接著，利用化學氣相沉積法形成一 介電層於所述導線結構上；再接著，旋塗一旋塗式玻璃於所 述介電層上；最後，固化所述旋塗式玻璃。 圖式簡要說明： 圖一爲本發明實施例之導電層間介電層結構剖面示意 0。 圖號說明： 10·基板 20-金屬導線 30-介電層 40-旋塗式玻璃（SOG) 發明詳細說明： 本發明可應用在半導體製程中製作積體電路中導電層間 介電層（dielectric layer)的方法，係一種利用降低導線結構 與介電層間的附著力（adhesion)，改進習知技術中因熱脹冷 縮效應而導致介電層及旋塗式玻璃（Spin On Glass; S0G) 間存在空隙（voids)的方法。以下之實施例將利用來闡述 本發明之技術手段： 首先，請參閱圖一，提供一已完成前段製程的半導體基 板，形成一含鋁金屬之導電層於所述基板上，所述含 鋁金屬可爲鋁、鋁銅合金或銘矽銅合金；接著，利用微影技 術（photolithography technology)及乾式触刻法（dry etch) ^^^1 ^^1 ^^^1 ^^—^1 K ml —^ϋ 11 _ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ式7公釐） '~~~ - 4369 6 8 A7 B7 五、發明説明（f ) 定義並蝕刻所述金屬導電層，形成金屬導線20結構，且於 蝕刻金屬導電層時通入三氟甲烷（CHF3)氣體，所述氣體 可以其他含氟氣體取代，其流量係介於2 seem至5 seem之 間；然後，形成一介電層30於所述金屬導線20結構上，所 述介電層30係利用電漿增強化學氣相沉積法（Plasma Enhanced Chemical Vapor Deposition ; PECVD)沉積之氧化 層，通常簡稱PEOX，其厚度係介於200A至300A之間， 其目的在防止水氣侵入金屬導線20而導致金屬導線20結構 被腐蝕;再接著，旋塗一旋塗式玻璃40於所述介電層30上， 增加晶片表面之平坦程度；最後，經由熱處理固化所述旋塗 式玻璃，其固化溫度約在400°C，反應時間介於約4小時之 間，固化處理是爲了去除用來溶解介電材質的溶劑，完成之 後一種用來填補_介電層凹陷區域的平坦化製程便大功告 成。 上述蝕刻含鋁金屬之導電層時通入三氟甲烷（CHF3) 氣體係爲本發明之重點，蝕刻時通入之CHF3氣體會與含鋁 金屬中的鋁（A1)進行反應，在金屬導線20之側邊形成氟 化鋁（A1FX)，而入正^^的存在可避免當金屬鋁暴露於大氣下 時氧化形成氧化鋁（A1203)，其目的在於降低金屬導線20 與所述介電層30間的附著力，因爲A1FX與所述介電層30間 的附著力小於Al2〇3與所述介電層30間的附著力。隨著金 屬導線20與介電層30之間附著力減小，可以避免如習知 技藝中當金屬導線20與介電層30間有較強的附著力存在 時，經過旋塗式玻璃40的固化熱處理之後，晶片溫度下降， _ ^.1 裝-- (請先閱讀背面之注意事項再填寫本頁) ,11 經濟部智慧財產局員工消费合作社印製 本紙張尺度適用中國國家揉準（CNS ) A4規格（2IOX2#公釐） 4 3 6 9 6 8 A7 __B7 五、發明説明（ί) 金屬導線20向內縮小而將介電層30 —起帶向內縮，而導致 附著力小的PEOX與旋塗式玻璃40間在金屬導線20側面 位置（因爲側邊熱脹冷縮的效應較明顯）剝離形成空隙 (voids)的情形。因爲當金屬導線20與介電層30間附著 力較弱時，介電層30不會被金屬導線20帶向內縮，就不會 造成介電層30與旋塗式玻璃40間剝離形成空隙的現象，進 而降低了後續製程中產生產品可靠度與良率的問題。 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明的範圍，因此熟知此技藝的人士應能明瞭，適當而作 些微的改變與調整，仍將不失本發明之要義所在，亦不脫離 本發明之精神和範圍1故都應視爲本發明的進一步實施狀 況。謹請貴審查委員明鑑，並祈惠准，是所至禱。 I—I- - i - s* nn m nn J—J. 3t^、v一w <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS M4規格（210 X 2幻公釐）A7 B7 _ V. Description of the invention (/) Field of invention: _ (Please read the precautions on the back before filling out this page) The present invention discloses a method for making a dielectric layer between conductive layers in a integrated circuit, especially a method for eliminating Spin-on-glass (SOG) method and voids between dielectric layers. Background of the invention: Near women, with the development of integrated circuits in the direction of smaller size and higher enthusiasm, the internal wiring requirements of integrated circuits have also evolved from the simple two- and three-layer structure in the past to four or more layers The Multilevel Interconnects process makes the flatness of each layer in the integrated circuit directly affect the difficulty of manufacturing a multilayer stacking structure, which has become one of the important considerations in modern semiconductor manufacturing processes. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The application of spin-on-glass (SOG) is a technique commonly used to locally flatten intermetal dielectric layers (IMDs). SOG is a fairly simple planarization technology, including two process stages of coating and curing. A spin-coating method is used to apply a liquid dielectric material with a very good trench filling ability to the wafer. The dielectric material of the cloth can follow the flow of the solvent on the surface of the wafer, so it can be easily filled into the structural grooves to achieve the purpose of local flattening. Then, the solvent in the spin-on glass is applied by heat treatment. Evaporate to increase the density of the spin-on glass and cure it to a structure similar to that of silicon dioxide (Si02). The flatness of the wafer surface will be better than that of chemical vapor deposition (CVD). The results obtained are still ideal. However, due to the application of spin-coated glass itself, particles can be caused: when the solvent is volatilized, the paper can be stripped. The paper size applies to Chinese national standards (CNS > A4 size (210X297 mm) 4369 6 8 A7 B7. 5. Description of the invention (> ) Out gassing occurs, and water absorption will occur in subsequent processes, which will cause the surface of the dielectric layer to be uneven. Now spin-on glass (SOG), which is widely used in the semiconductor industry, is usually used for The sandwich type structure is adopted to ensure the physical properties and chemical properties of the spin-on glass. The 8102 deposited by the two-layer chemical vapor deposition method (CVD) is used to sandwich the spin-on glass. The CVD-Si02 is generally formed by using a Plasma Enhance Chemical Vapor Deposition (PECVD) method with the advantage of low temperature. However, the disadvantage of this method is that because the metal wire has a large expansion coefficient, The phenomenon of thermal expansion and contraction will be more obvious. After the curing heat treatment of the spin-on glass, the temperature of the wafer will decrease, and the metal wire will shrink inward. However, because CVD-Si02 has strong adhesion between metal wires, CVD-Si02 will be brought inward by the metal wires when the metal wires shrink inward, but CVD-Si02 and SOG-SiO / ^ The adhesion is not enough, with the inward shrinkage of CVD-Si02K, resulting in CVD-SiCy ^ SOG-Si02 from the side of the metal wire (because the effect of thermal expansion and contraction of the side is more obvious) peel to form voids, and Product reliability and yield problems are generated. Therefore, in order to solve the problems caused by the conventional technology, the present invention provides a method for manufacturing a dielectric layer between conductive layers in an integrated circuit to eliminate the problem. Formation of interlayer dielectric gaps. Summary of the invention: The main purpose of the present invention is to provide a method for making a conductive interlayer dielectric layer in an integrated circuit, by reducing the adhesion between the conductive layer and the interlayer, and avoiding the application of this paper scale. China National Standards (CMS) A4 specification (21〇X: 2i7 mm) Body-I--(Please read the precautions on the back before filling out this page) Printing A7 4369 6 8 Description of the invention (j) The formation of gaps between the dielectric layers improves the reliability and yield of the product. The present invention uses the following steps to achieve the above-mentioned purpose: First, a semiconductor substrate having completed the previous process is provided, and a conductive layer is formed on the semiconductor substrate. On the substrate; then, adding a gas which can reduce the adhesion between the wire structure and the dielectric layer when the conductive layer is etched; and then, forming a dielectric layer on the wire structure by a chemical vapor deposition method; Then, a spin-on glass is spin-coated on the dielectric layer; finally, the spin-on glass is cured. Brief description of the drawings: FIG. 1 is a schematic cross-sectional view of a structure of a conductive interlayer dielectric layer according to an embodiment of the present invention. Description of the drawing number: 10 · substrate 20-metal wire 30-dielectric layer 40-spin-on glass (SOG) Detailed description of the invention: The present invention can be applied to the fabrication of conductive interlayer dielectric layers in integrated circuits in semiconductor processes ) Method is to reduce the adhesion between the wire structure and the dielectric layer (adhesion), to improve the thermal expansion and contraction effect caused by the conventional technology caused by the dielectric layer and the spin-on glass (S0G). There are voids. The following embodiments will be used to illustrate the technical means of the present invention: First, please refer to FIG. 1 to provide a semiconductor substrate that has completed the previous process, and form a conductive layer containing aluminum metal on the substrate. It can be aluminum, aluminum-copper alloy or silicon-silicon-copper alloy; then, using photolithography technology and dry etch ^^^ 1 ^^ 1 ^^^ 1 ^^ — ^ 1 K ml — ^ Ϋ 11 _ (Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is printed in accordance with China National Standard (CNS) A4 (210 × 7mm) '~~ ~-4369 6 8 A7 B7 V. Description of the invention (f) Define and etch the metal conductive layer to form a metal wire 20 structure, and pass through trifluoromethane (CHF3) gas when the metal conductive layer is etched. The gas can be Other fluorine-containing gases are substituted, and the flow rate is between 2 seem and 5 seem; then, a dielectric layer 30 is formed on the metal wire 20 structure, and the dielectric layer 30 is made of a plasma-enhanced chemical vapor phase. Deposition method (Plasma Enhanced Chemical Vapor Deposition; PECVD), usually referred to as PEOX, has a thickness between 200A and 300A. Its purpose is to prevent water vapor from invading the metal wire 20 and causing the structure of the metal wire 20 to be corroded. Then, a spin coating is performed. The coated glass 40 is on the dielectric layer 30 to increase the flatness of the wafer surface. Finally, the spin-coated glass is cured by heat treatment, the curing temperature is about 400 ° C, and the reaction time is between about 4 hours. The curing process is to remove the solvent used to dissolve the dielectric material. After completion, a planarization process to fill the recessed area of the dielectric layer is completed. The introduction of trifluoromethane (CHF3) gas system when etching the conductive layer of aluminum-containing metal is the focus of the present invention. The CHF3 gas introduced during etching will react with aluminum (A1) in the aluminum-containing metal. Aluminum fluoride (A1FX) is formed on the side, and the presence of Zn ^^ prevents the aluminum oxide from oxidizing to form aluminum oxide (A1203) when the aluminum is exposed to the atmosphere. The adhesion between A1FX and the dielectric layer 30 is smaller than the adhesion between Al203 and the dielectric layer 30. As the adhesion between the metal wire 20 and the dielectric layer 30 decreases, it can be avoided that when the strong adhesion between the metal wire 20 and the dielectric layer 30 exists in the conventional art, After curing and heat treatment, the temperature of the wafer decreases, _ ^ .1 pack-(Please read the precautions on the back before filling out this page), 11 Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs This paper is printed in accordance with China's national standard (CNS ) A4 specification (2IOX2 # mm) 4 3 6 9 6 8 A7 __B7 V. Description of the invention (ί) The metal wire 20 shrinks inward and the dielectric layer 30 shrinks inward, leading to a small adhesion PEOX In the case where it is peeled off from the spin-coated glass 40 at the side of the metal wire 20 (because the effect of thermal expansion and contraction of the side is more obvious), voids are formed. Because when the adhesion between the metal wire 20 and the dielectric layer 30 is weak, the dielectric layer 30 will not be pulled inwardly by the metal wire 20, and it will not cause the dielectric layer 30 and the spin-on glass 40 to form a gap. This reduces the problems of product reliability and yield in subsequent processes. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention. Therefore, those skilled in the art should be able to understand that making appropriate changes and adjustments will still not lose the essence of the present invention. Without departing from the spirit and scope of the present invention, it should be regarded as a further implementation of the present invention. I would like to ask your reviewers to make a clear reference and pray for your sincere prayer. I—I--i-s * nn m nn J—J. 3t ^, v_w < Please read the notes on the back before filling out this page) Consumption Cooperation between Employees and Intellectual Property Bureau of the Ministry of Economic Affairs Applicable to Chinese national standard (CNS M4 specification (210 X 2 magic mm)