JPS6294937A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS6294937A
JPS6294937A JP23573185A JP23573185A JPS6294937A JP S6294937 A JPS6294937 A JP S6294937A JP 23573185 A JP23573185 A JP 23573185A JP 23573185 A JP23573185 A JP 23573185A JP S6294937 A JPS6294937 A JP S6294937A
Authority
JP
Japan
Prior art keywords
silicon
polycrystalline silicon
substrate
melting point
high melting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23573185A
Other languages
Japanese (ja)
Other versions
JPH0682641B2 (en
Inventor
Yukinobu Murao
幸信 村尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60235731A priority Critical patent/JPH0682641B2/en
Publication of JPS6294937A publication Critical patent/JPS6294937A/en
Publication of JPH0682641B2 publication Critical patent/JPH0682641B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To enable an even silicide layer to be formed by a method wherein the surface of substrate silicon and polycrystalline silicon is etched in Ar plasma atmosphere before the surface is coated with high melting point metal to remove the damge layers formed by the preceding etching process. CONSTITUTION:A gate oxide film 11 is formed on a silicon semiconductor substrate 10; a gate polycrystalline silicon substrate 12 is formed on the oxide film 11; and the surface including the silicon electrode 12 is coated with a vapor grown insulating film 13. First, the vapor grown insulating film 13 is etched by anisotropical dry etching process using a reactive gas to form sidewalls 13a on the sides of polycrystalline silicon electrode 12. At this time, damaged layers 14 and 14a are formed respectively on the diffused layers of source drain and the polycrystalline silicon of gate electrode 12. Second, the damaged layers 14 and 14a are removed by etching process in Ar atmosphere to be coated successively with high melting point metal such as Ti film 16 etc. Finally not yet reacted Ti is removed by silicification in inert gas atmosphere. Through these procedures, an even silicide layer 17 can be formed on the substrate silicon 10 and the polycrystalline silicon 12.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路装置の製造方法に関し、特に
、高融点金属ノリサイド層を形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and particularly to a method for forming a high melting point metal nolicide layer.

〔従来の技術〕[Conventional technology]

従来、シリコン半導体集積回路装置の、たとえは拡赦層
領域の7リサイド化は、拡散層上の絶縁物を反応性ガス
を用いたドライエツチング法で除去した後、高融点金属
を被着し熱処理法等によりシリサイド層を形成してきた
Conventionally, in silicon semiconductor integrated circuit devices, for example, 7 reciding of the expansion layer region involves removing the insulator on the diffusion layer by dry etching using a reactive gas, then depositing a high-melting point metal and heat-treating. The silicide layer has been formed by methods such as the method.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の高融点金−ノリサイド)−の形成方法は
、高融点金属被着前に反応性ガスによるドライエツチン
グ法で、ノリサイド化される領域にり°7−ジが与えら
れる為に/リコン表面に7リサイド化しにくいI−が形
成され、均一なノリサイド層が出来ないという問題があ
った。
The above-mentioned conventional method for forming high melting point gold (noride) is a dry etching method using a reactive gas before depositing the high melting point metal, which imparts a degree of damage to the area to be converted to noride. There was a problem in that I-, which is difficult to convert into silicide, was formed on the surface, making it impossible to form a uniform nollyside layer.

本発明の目的は、シリコン基板及び多結晶シリコン上に
均一なシリサイドJ−を形成する半導体集積回路装置の
製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device in which uniform silicide J- is formed on a silicon substrate and polycrystalline silicon.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明の半導体集積回路の製造方法は、シリコン上ある
いは、多結晶シリコン上に高融照会JI!4を被着し、
熱処理法等によりノリサイド層を形成する場合、高融点
金属被着する際Arプラズマ中で前記のシリコン基板あ
るいは、多結晶シリコン表面をエツチングした後高融照
会^を被着することにより構成される。
The method for manufacturing a semiconductor integrated circuit of the present invention is a method for manufacturing a semiconductor integrated circuit on silicon or polycrystalline silicon. 4 is applied,
When a noride layer is formed by a heat treatment method or the like, it is formed by etching the silicon substrate or polycrystalline silicon surface in Ar plasma when depositing a high melting point metal, and then depositing a high melting point metal.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。第1図(a)〜(dlは本発明の一実施例を説明する
ために工程順に示した半導体素子の断面図である。
Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(dl) are cross-sectional views of a semiconductor device shown in order of steps to explain an embodiment of the present invention.

”まず、第1図(a)に示すように、シリコン半導体基
板10上にはゲート酸化膜11が形成され、ゲート改化
展上にはケート多結晶7リコン12が形成されゲート多
結晶シリコン電極を含む表面には〜気相成長絶縁膜13
を被着する。
First, as shown in FIG. 1(a), a gate oxide film 11 is formed on a silicon semiconductor substrate 10, a gate polycrystalline silicon 12 is formed on the gate reforming layer, and a gate polycrystalline silicon electrode is formed. ~ vapor phase growth insulating film 13 on the surface including
be coated with.

次に、第1図(b)に示すように、反応性ガスを用いる
異方性ドライエツチングで気相成長絶縁膜13をエツチ
ングし、ゲート電極である多結晶シリコン12の側面に
l1111m l 3 aを形成する。この際、反応性
ガスを用いたエツチングによシソース・ドレインの拡散
AJ上及びゲート電極12の多結晶7リコン上にはダメ
ージl−14及び14aが形成される。
Next, as shown in FIG. 1(b), the vapor phase grown insulating film 13 is etched by anisotropic dry etching using a reactive gas, and a layer of l1111ml l3a is formed on the side surface of the polycrystalline silicon 12, which is the gate electrode. form. At this time, damages 1-14 and 14a are formed on the source/drain diffusion AJ and on the polycrystalline silicon of the gate electrode 12 by etching using a reactive gas.

次に、Ar雰囲気中でエツチングを行ないダメージ層1
4及び14aを除去し、ひき続きTi膜16等の高融点
金属を被着し、第1図(C)の状態とする。
Next, the damaged layer 1 is etched in an Ar atmosphere.
4 and 14a are removed, and a high melting point metal such as a Ti film 16 is subsequently deposited to form the state shown in FIG. 1(C).

次に、第1図(d)に示すように、不活性ガス雰囲気中
で7リサイド化を行ない、未反応Tiを除去して基板7
リコン上及び多結晶シリコン上に7リサイド層17を形
成する。
Next, as shown in FIG. 1(d), 7-reciding is performed in an inert gas atmosphere to remove unreacted Ti and remove the substrate 7.
A 7-reside layer 17 is formed on the silicon and polycrystalline silicon.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明はノリサイド化法により、
シリコン基板及び多結晶シリコン上に7リサイド層を形
成する場合、基板シリコン上及び多結晶シリコン上に、
高融点金属を被着する直前に、Arプラズマ中で基板シ
リコン及び多結晶シリコン表面をエツチングし、前のエ
ツチング時に生じたダメージ層を除去することにより均
一なシリサイド層を形成できる効果がある。
As explained above, the present invention uses the noricidation method to
When forming a 7 reside layer on a silicon substrate and polycrystalline silicon, on the substrate silicon and polycrystalline silicon,
Immediately before depositing the high melting point metal, the surfaces of the substrate silicon and polycrystalline silicon are etched in Ar plasma to remove the damaged layer produced during the previous etching, thereby making it possible to form a uniform silicide layer.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al〜(dlは、本発明の一実施例を説明する
ために工程順に示した半導体素子の断面図である。 10・・・・・・7リコン半導体基板、11・・・・・
・ゲートは化膜、12・・・・・・ゲート多結晶7リコ
/電極、13・・・・・・気相成長酸化膜、14 、1
4 a °°゛・°ダメージ層・15・・・・・・Ar
プラズマ、16・・・・・・Ti膜、17・・・・・−
チタン7リサイド(’f’iSi□)層。 代理人 弁理士  内 原   音 躬 / 図
FIG. 1 (al to (dl) are cross-sectional views of a semiconductor element shown in the order of steps to explain an embodiment of the present invention. 10...7 silicon semiconductor substrate, 11...・
・Gate is a chemical film, 12... Gate polycrystalline 7 Lico/electrode, 13... Vapor phase growth oxide film, 14, 1
4 a °°゛・°damage layer・15...Ar
Plasma, 16...Ti film, 17...-
Titanium 7 reside ('f'iSi□) layer. Agent Patent Attorney Otomi Uchihara / Illustration

Claims (1)

【特許請求の範囲】[Claims]  基板シリコンと多結晶シリコン上に高融点金属を被着
し熱処理法等により前記基板シリコン上あるいは、多結
晶シリコン上に前記高融点金属のシリサイド層を形成す
る工程を有する半導体集積回路装置の製造方法において
、前記高融点金属を被着するに先立ちArプラズマ中で
前記基板シリコンと多結晶シリコン表面をエッチングす
ることを特徴とする半導体集積回路装置の製造方法。
A method for manufacturing a semiconductor integrated circuit device, comprising the steps of depositing a high melting point metal on a silicon substrate and polycrystalline silicon, and forming a silicide layer of the high melting point metal on the silicon substrate or polycrystalline silicon by heat treatment or the like. A method for manufacturing a semiconductor integrated circuit device, characterized in that the surfaces of the substrate silicon and polycrystalline silicon are etched in Ar plasma prior to depositing the high melting point metal.
JP60235731A 1985-10-21 1985-10-21 Method for manufacturing semiconductor integrated circuit device Expired - Lifetime JPH0682641B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60235731A JPH0682641B2 (en) 1985-10-21 1985-10-21 Method for manufacturing semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60235731A JPH0682641B2 (en) 1985-10-21 1985-10-21 Method for manufacturing semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6294937A true JPS6294937A (en) 1987-05-01
JPH0682641B2 JPH0682641B2 (en) 1994-10-19

Family

ID=16990393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60235731A Expired - Lifetime JPH0682641B2 (en) 1985-10-21 1985-10-21 Method for manufacturing semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0682641B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5407837A (en) * 1992-08-31 1995-04-18 Texas Instruments Incorporated Method of making a thin film transistor
US5926705A (en) * 1995-10-19 1999-07-20 Nec Corporation Method for manufacturing a semiconductor device with stabilization of a bipolar transistor and a schottky barrier diode
US6562699B1 (en) 1997-04-25 2003-05-13 Sharp Kabushiki Kaisha Process for manufacturing semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5768033A (en) * 1980-10-16 1982-04-26 Toshiba Corp Manufacture of semiconductor device
JPS5799775A (en) * 1980-12-12 1982-06-21 Toshiba Corp Manufacture of semiconductor device
JPS57124477A (en) * 1981-01-26 1982-08-03 Toshiba Corp Manufacture of semiconductor device
JPS5818965A (en) * 1981-07-28 1983-02-03 Toshiba Corp Manufacture of semiconductor device
JPS6052044A (en) * 1983-05-06 1985-03-23 テキサス インスツルメンツ インコ−ポレイテツド Method of forming metal silicide
JPS6197839A (en) * 1984-10-18 1986-05-16 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5768033A (en) * 1980-10-16 1982-04-26 Toshiba Corp Manufacture of semiconductor device
JPS5799775A (en) * 1980-12-12 1982-06-21 Toshiba Corp Manufacture of semiconductor device
JPS57124477A (en) * 1981-01-26 1982-08-03 Toshiba Corp Manufacture of semiconductor device
JPS5818965A (en) * 1981-07-28 1983-02-03 Toshiba Corp Manufacture of semiconductor device
JPS6052044A (en) * 1983-05-06 1985-03-23 テキサス インスツルメンツ インコ−ポレイテツド Method of forming metal silicide
JPS6197839A (en) * 1984-10-18 1986-05-16 Fujitsu Ltd Manufacture of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5407837A (en) * 1992-08-31 1995-04-18 Texas Instruments Incorporated Method of making a thin film transistor
US5926705A (en) * 1995-10-19 1999-07-20 Nec Corporation Method for manufacturing a semiconductor device with stabilization of a bipolar transistor and a schottky barrier diode
US6562699B1 (en) 1997-04-25 2003-05-13 Sharp Kabushiki Kaisha Process for manufacturing semiconductor device
US7135386B2 (en) 1997-04-25 2006-11-14 Sharp Kabushiki Kaisha Process for fabricating a semiconductor device

Also Published As

Publication number Publication date
JPH0682641B2 (en) 1994-10-19

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