JPS5852330B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5852330B2
JPS5852330B2 JP12350076A JP12350076A JPS5852330B2 JP S5852330 B2 JPS5852330 B2 JP S5852330B2 JP 12350076 A JP12350076 A JP 12350076A JP 12350076 A JP12350076 A JP 12350076A JP S5852330 B2 JPS5852330 B2 JP S5852330B2
Authority
JP
Japan
Prior art keywords
wiring
film
silicon oxide
layer
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12350076A
Other languages
Japanese (ja)
Other versions
JPS5348675A (en
Inventor
良司 阿部
誠 芹ケ野
忠一 高田
順博 内山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12350076A priority Critical patent/JPS5852330B2/en
Publication of JPS5348675A publication Critical patent/JPS5348675A/en
Publication of JPS5852330B2 publication Critical patent/JPS5852330B2/en
Expired legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

【発明の詳細な説明】 本発明は合成樹脂を用いた半導体装置の製造方法に関し
、特に酸化シリコン皮膜の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device using a synthetic resin, and particularly to a method for forming a silicon oxide film.

従来、酸化シリコン膜は気相成長法、熱酸化法等比較的
高温で形成されるためアルミニラμAt)等の低融点金
属を用いる半導体装置に適用する場合、合金化等の不都
合があった。
Conventionally, silicon oxide films have been formed at relatively high temperatures using vapor phase growth methods, thermal oxidation methods, etc., and therefore, when applied to semiconductor devices using low melting point metals such as aluminum oxide (μAt), there have been problems such as alloying.

本発明は、比較的低温で容易に酸化シリコン皮膜を形成
する方法を提供するもので、シリコン樹脂皮膜を酸素プ
ラズマ照射により、酸化シリコン皮膜に変換することを
特徴とする。
The present invention provides a method for easily forming a silicon oxide film at a relatively low temperature, and is characterized by converting a silicon resin film into a silicon oxide film by irradiating oxygen plasma.

本発明は、シリコン樹脂皮膜に酸素プラズマを照射する
とシリコン酸化膜に変換することを発見したことに基づ
くもので、次の実1験例から本発明の有効性を明らかに
する。
The present invention is based on the discovery that when a silicon resin film is irradiated with oxygen plasma, it is converted into a silicon oxide film.The effectiveness of the present invention will be clarified from the following experimental example.

シリコン半導体結晶等の基板にシリコン樹脂を厚さ約2
,000人程度に塗布し、900Gで15分間、300
〜450℃で10〜30分間加熱処理を行ない、シリコ
ン樹脂膜を硬化させる。
Apply silicon resin to a thickness of about 2 cm on a substrate such as silicon semiconductor crystal.
,000 people, 900G for 15 minutes, 300g
Heat treatment is performed at ~450° C. for 10 to 30 minutes to harden the silicone resin film.

このように便化させたシリコン樹脂皮膜は通常ノシリコ
ン酸化膜のエツチング液であるフン酸エツチング液には
エツチングされない。
The silicone resin film thus treated is not etched by a hydrofluoric acid etching solution, which is normally an etching solution for silicon oxide films.

ところが該基板を酸素ガス圧I Torr、出力ioo
wで発生する酸素プラズマ雰囲気中に約15分間放置す
ると皮膜の厚さはi、oooλ程度と約1/2の厚さに
なりフッ酸系エツチング液でエツチングされる。
However, when the substrate is exposed to oxygen gas pressure I Torr and output ioo
When the film is left in an oxygen plasma atmosphere generated by W for about 15 minutes, the thickness of the film becomes about 1/2, i, oooλ, and is etched with a hydrofluoric acid etching solution.

該皮膜のエツチング速度は、液相成長シリコン酸化膜、
リン・シリケート・ガラスと同程度の1分間約5,00
0人の速さでエツチングされる。
The etching rate of the film is as follows:
Approximately 5,000 yen per minute, the same as phosphorus silicate glass
It is etched at the speed of 0 people.

シリコン樹脂被膜全面を酸化被膜に変換する場合、シリ
コン樹脂皮膜の厚さは2,000Å以下が望ましい。
When converting the entire surface of the silicone resin film into an oxide film, the thickness of the silicone resin film is preferably 2,000 Å or less.

シリコン樹脂皮膜の厚さを2,0OOA以上とした場合
、酸素プラズマ照射によって変質した皮膜にクラックが
生ずる。
If the thickness of the silicone resin film is 2.0 OOA or more, cracks will occur in the film that has been altered by oxygen plasma irradiation.

酸素プラズマ照射時の基板温度は最高200℃であり、
低温でシリコン酸化膜が得られる。
The maximum substrate temperature during oxygen plasma irradiation is 200°C,
Silicon oxide film can be obtained at low temperature.

次に本発明をいわゆる多層配線の層間絶縁膜に適用した
実施例により図を参照して説明する。
Next, an embodiment in which the present invention is applied to an interlayer insulating film of a so-called multilayer wiring will be described with reference to the drawings.

従来、この多層配線は第1図に示すように、半導体基板
1上にアルミニウム(At)を蒸着して、フォト・エツ
チングにより所望の配線パターンの第1層配線2を形成
し、その上に低温気相成長等により、二酸化硅素(S
102)絶縁層3を設け、その絶縁層にスルー・ホール
等を形成した後、再びAtを蒸着して、フォト・エツチ
ングにより所望の配線パターンの第2層配線4を形成し
、必要ならば更に前述の工程を繰返して多層配線を形成
するものであった。
Conventionally, this multilayer wiring is made by depositing aluminum (At) on a semiconductor substrate 1, forming a first layer wiring 2 with a desired wiring pattern by photo-etching, and then applying low-temperature etching on top of the first layer wiring 2, as shown in FIG. Silicon dioxide (S
102) After providing the insulating layer 3 and forming through holes etc. in the insulating layer, At is deposited again and the second layer wiring 4 of the desired wiring pattern is formed by photo-etching, and further etching is performed if necessary. Multilayer wiring was formed by repeating the above steps.

従って、第1層配線2の角部分の絶縁層3及び第2配線
層4は、急激な段部により他の部分より薄くなり、絶縁
不良及び第2層配線4の断線が発生し易い欠点があった
Therefore, the insulating layer 3 and the second wiring layer 4 at the corner portions of the first layer wiring 2 are thinner than the other portions due to the sharp stepped portions, which has the disadvantage that poor insulation and disconnection of the second layer wiring 4 are likely to occur. there were.

この欠点を除く為には、必要以上に絶縁層3及び第2層
配線4を厚くしなければならず、それによって一層凹凸
が激しくなるので、3層、4層等の多層配線を施す場合
に再び前述の欠点が現わ札信頼性が低下するものであっ
た。
In order to eliminate this drawback, it is necessary to make the insulating layer 3 and the second layer wiring 4 thicker than necessary, which makes the unevenness even more severe. Once again, the above-mentioned drawbacks appeared, reducing the reliability of the bill.

また配線層のAtは、比較的低温で溶融、合金化するた
め配線層間絶縁膜は比較的低温で形成する必要がある。
Further, since At in the wiring layer is melted and alloyed at a relatively low temperature, the wiring interlayer insulating film must be formed at a relatively low temperature.

このため、層間絶縁膜としてシリコン樹脂、ポリイミド
樹脂等の合成樹脂を用いる方法が提案されているが、フ
ォト・エツチングにより、コンタクト窓を形成する際、
合成樹脂の強いアルカリ性エツチング液により、フォト
レジスト・パターンが不明瞭となり、またAt配線及び
半導体基板がアルカリイオンに汚染される欠点がある。
For this reason, methods using synthetic resins such as silicone resin and polyimide resin as interlayer insulating films have been proposed, but when forming contact windows by photo-etching,
Due to the strong alkaline etching solution for synthetic resins, the photoresist pattern becomes unclear and the At wiring and semiconductor substrates are contaminated with alkali ions.

本発明を配線層間絶縁膜に適用すれば、上述の欠点は解
決される。
If the present invention is applied to a wiring interlayer insulating film, the above-mentioned drawbacks can be solved.

すなわち、第2図aに示す如く、半導体基板11上にア
ルミニウム(At)を蒸着して、フォトエツチングによ
り所望の配線パターンの第1層配線12を形成した後、
シリコン樹脂を塗布し、前記第1層配線12を被覆し、
90℃で約15分間加熱処理を行ない、シリコン樹脂皮
膜15を硬化させる。
That is, as shown in FIG. 2a, after aluminum (At) is deposited on the semiconductor substrate 11 and the first layer wiring 12 of a desired wiring pattern is formed by photoetching,
Applying silicone resin to cover the first layer wiring 12,
Heat treatment is performed at 90° C. for about 15 minutes to harden the silicone resin film 15.

該シリコン樹脂は、粘性のある液状であるため、第4層
配線120段差部を埋め合わせ全体として、なだらかな
表面を形成する。
Since the silicone resin is a viscous liquid, it compensates for the stepped portion of the fourth layer wiring 120 and forms a smooth surface as a whole.

次に、該基板に酸素ガス圧I Torr、出力100W
で発生する酸素プラズマを約15分間照射して、前記シ
リコン樹脂皮膜15をシリコン酸化膜16に変換する。
Next, the substrate was subjected to an oxygen gas pressure of I Torr and an output of 100 W.
The silicone resin film 15 is converted into a silicon oxide film 16 by irradiating the silicone resin film 15 with oxygen plasma generated for about 15 minutes.

続いて第2図すに示す如く、フオスフオ・シリケート・
ガラス(PSG)層を気相成長するか、又は液相酸化シ
リコン17を塗布する。
Next, as shown in Figure 2, phosphorus silicate
A glass (PSG) layer is grown in vapor phase or liquid phase silicon oxide 17 is applied.

これは変質したシリコン酸化膜16が気相成長シリコン
酸化膜と異なり多孔性があるためPSG等を被覆するこ
とによって、信頼性を上げるものである。
This is because the altered silicon oxide film 16 is porous unlike a vapor-phase grown silicon oxide film, so by covering it with PSG or the like, reliability is improved.

次に第2図Cに示す如く、前記PSG又はシリコン酸化
皮膜17及び酸素プラズマ煕射によるシリコン酸化膜1
6から成る絶縁層に、通常のシリコン酸化膜のフォト・
エツチングと同様にして、配線のコンタクト窓18を形
成しA4を蒸着し、フォト・エツチングにより所望の配
線パターンの第2層配線14を形成する。
Next, as shown in FIG. 2C, the PSG or silicon oxide film 17 and the silicon oxide film 1 formed by oxygen plasma
A photo film of ordinary silicon oxide film is applied to the insulating layer consisting of 6.
In the same manner as etching, a contact window 18 for wiring is formed, A4 is deposited, and a second layer wiring 14 having a desired wiring pattern is formed by photo-etching.

上述の如く、多層配線の層間絶縁膜を本発明により形成
すれば、容易に配線層のコンタクト窓の形成ができ、ま
たAt配線層の断線を防止することができる利点がある
As described above, if the interlayer insulating film of the multilayer wiring is formed according to the present invention, contact windows in the wiring layer can be easily formed, and there are advantages that disconnection of the At wiring layer can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の多層配線法を示す図、第2図は本発明に
よる多層配線の一部工程図を示す。 11・・・・・・半導体基板、12・・・・・・第1層
配線、14・・・・・・第2層配線、15・・・・・・
シリコン樹脂皮膜、16・・・・・・変質したシリコン
酸化膜、17・・・・・・PSG膜は気相成長シリコン
酸化膜、3・・・・・・気相成長シリコン酸化膜。
FIG. 1 is a diagram showing a conventional multilayer wiring method, and FIG. 2 is a partial process diagram of a multilayer wiring according to the present invention. 11... Semiconductor substrate, 12... First layer wiring, 14... Second layer wiring, 15...
Silicon resin film, 16... Altered silicon oxide film, 17... PSG film is vapor phase grown silicon oxide film, 3... Vapor phase grown silicon oxide film.

Claims (1)

【特許請求の範囲】[Claims] 1 シリコン樹脂皮膜を酸素プラズマ照射により酸化シ
リコン皮膜に変換することを特徴とする半導体装置の製
造方法。
1. A method for manufacturing a semiconductor device, which comprises converting a silicone resin film into a silicon oxide film by oxygen plasma irradiation.
JP12350076A 1976-10-15 1976-10-15 Manufacturing method of semiconductor device Expired JPS5852330B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12350076A JPS5852330B2 (en) 1976-10-15 1976-10-15 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12350076A JPS5852330B2 (en) 1976-10-15 1976-10-15 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5348675A JPS5348675A (en) 1978-05-02
JPS5852330B2 true JPS5852330B2 (en) 1983-11-22

Family

ID=14862147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12350076A Expired JPS5852330B2 (en) 1976-10-15 1976-10-15 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5852330B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6230335A (en) * 1985-07-31 1987-02-09 Fujitsu Ltd Manufacture of semiconductor device
JPH05243577A (en) * 1992-02-26 1993-09-21 Seiko Epson Corp Manufacture of thin film transistor

Also Published As

Publication number Publication date
JPS5348675A (en) 1978-05-02

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