JPS59227185A - Method of producing printed circuit board - Google Patents
Method of producing printed circuit boardInfo
- Publication number
- JPS59227185A JPS59227185A JP10127083A JP10127083A JPS59227185A JP S59227185 A JPS59227185 A JP S59227185A JP 10127083 A JP10127083 A JP 10127083A JP 10127083 A JP10127083 A JP 10127083A JP S59227185 A JPS59227185 A JP S59227185A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- copper foil
- pattern
- etching
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、微細パターンを容易に得ることが出入る印M
l配勝板の#遺伝に関す/)0印桐配線板の一線巾、線
間隔はLSIの高集積化にともない1丁ま丁細くなって
いるoシフ0為し、従来の製造方法では、例えば、銅張
り積層板にエツチングしてパターン【形敢丁ル硼台、1
00μmが加工限界となり、これ以下の腺巾では。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for easily obtaining a fine pattern by using a mark M that can be moved in and out.
Regarding #heredity of the distribution board/)0 The line width and line spacing of the paulownia wiring board have become narrower and narrower with the increasing integration of LSIs. Therefore, in the conventional manufacturing method, For example, etching a pattern on a copper-clad laminate
00μm is the processing limit, and if the gland width is less than this.
断線やショートか発生し易くなる。Disconnection or short circuits are more likely to occur.
こnは銅張積層板製造工程において発生する銅箔面のへ
こみ、キズなどが原因でるゐ。lた、巌巾、線間隔が5
0μm位になると銅張積層板表面の微小な凹凸fうねり
により絨巾梢度か問題となってくゐ。This is caused by dents and scratches on the copper foil surface that occur during the manufacturing process of copper-clad laminates. 1, width, line spacing is 5
When the thickness becomes about 0 μm, the carpet thickness becomes a problem due to minute irregularities and waviness on the surface of the copper-clad laminate.
また、通常銅箔が18〜65μmと厚いため100μ−
下のエツチングか非常に困難になる。5〜9μmQ銅箔
に用いnば内層回路用のエツチングは容易にな/)が、
表層Sは、スルホール内のめっきが附7Jl]芒扛るの
で、全体の銅の厚さは60〜40μmとなり100μm
以下のエツチングは非常に困姫でめゐ。このような事か
ら、エツチング法ではa<、必贅な部分にめっきにより
回路に形成するアディティブ法が微細パターンの形成に
迩丁心が、塊状では丞似弐面の粗度が大きく、また、不
必資な場所にもめっ@が析出する銅フリ現象があり、サ
ブトラクト法以上の微細パターンの形成かで@ない0そ
こで、5〜9μmの銅箔Y用いた銅張積層板にベースに
めっきにより必要な部分にめっきtした彼、ベースの博
い銅箔tクイックエッチするセミアディティブ法か微細
のノ(ターンに適している。しかし、この方法において
も、前記した銅張積層板自体Q)欠陥や特性に支配され
。In addition, since copper foil is usually thick at 18 to 65 μm, 100 μ-
Etching the bottom will be very difficult. If used for 5-9 μm Q copper foil, etching for inner layer circuits becomes easier.
Since the surface layer S is plated in the through holes, the total copper thickness is 60 to 40 μm, which is 100 μm.
The following etching is a very needy princess. For these reasons, the etching method is difficult to form fine patterns, and the additive method, in which circuits are formed by plating on the necessary areas, is difficult to form a fine pattern, but the roughness of the second surface is large in the case of blocky patterns, and it is difficult to form unnecessary patterns. There is a copper-free phenomenon in which plating precipitates even in areas where there is no material available, and it is not possible to form a finer pattern than the subtract method.Therefore, it is necessary to use a copper-clad laminate using 5-9 μm copper foil Y by plating the base. The semi-additive method of quick etching the wide copper foil on the base is suitable for fine turns (however, even with this method, the above-mentioned copper clad laminate itself Q) is free from defects and ruled by characteristics.
80μm以下の微細パターンの形成は因離でめゐ0
本発明はこのような点に鑑みてなさnたもので、@箔の
片面にめっきレジストに設け、銅のエツチング液に耐蝕
性のめる金属のめつき、銅のめり@電行い、回路パター
ン忙形成し、めっきレジストを除去し、回路パターン向
にグリフ−レグ塗型ね台せ刃口熱加圧した饋1穴あけ1
人内壁の銅めっ@電性い少なくともノくット鄭葡含む必
☆とさnゐ銅箔に工ゐ表面パターンに対応するエツチン
グレジスト電形成後鋼箔【エツチング丁ゐこと忙特徴と
するものである0
すなわち、従来技術に用いられゐ銅張積層板自体θ吋性
や欠陥に基〈限界に打破丁/Sために本発明では、回路
パターン葡形成丁ゐベース材料に銅箔を用いた。用いる
銅箔はステンレス似等に剥離可能なようにめっきした銅
箔でも良いし、丁でに引@はかされ′fC餉箔めゐいは
圧延ちれた#I76でもよい0第1凶に7F、丁ように
この銅箔1の片面に、フォトレジスト葡ラミネートし。It is difficult to form a fine pattern of 80 μm or less. The present invention was developed in view of these points. Plating, copper machining @electronic process, circuit pattern formation, plating resist removed, glyph-leg coating in the circuit pattern direction, set the blade edge heated and pressurized 1 hole 1
Copper plating of the internal wall must contain at least an electrically conductive surface pattern, and the etching resist corresponding to the surface pattern must be applied to the copper foil after electroforming the steel foil. In other words, the present invention uses copper foil as the base material for forming the circuit pattern, since the copper clad laminate used in the prior art has been used in the past due to its own properties and defects. there was. The copper foil to be used may be plated to make it removable, such as stainless steel, or it may be #I76 that has been peeled off with a knife or rolled. On the 7th floor, photoresist was laminated on one side of the copper foil 1.
焼付、現像丁ゐ等によりレジストパターン2電形成する
。次に、無1を解めっき、または、電気めっ@により雀
、ニッケル、千日など銅のエツチング液に耐蝕性のめる
金[5鷺めっきした恢。A resist pattern is formed by two electrodes by baking, developing, etc. Next, gold is coated with a corrosion-resistant copper etching solution such as sparrow, nickel, or nickel by electroplating or by electroplating.
銅めっき4′9thなう。レジスト2【剥離した俊。Copper plating 4'9th now. Resist 2 [Shun peeled off.
t444表面の接触処理電行なう。Contact treatment of the T444 surface is carried out.
次に第2図にボ)゛ようeここのようにして形成した回
路パターン5を市する銅箔1に衣1〜としてパターンに
内側にl’im回路板6と共に、j繭+aj位厘次め葡
し、グリプレグ6忙ブトして槓層接盾する。さらに、穴
あけ、スルーホールめっ@電行なう。次に、大同パッド
部、必菅とさf′L、/)銅箔による表面パターンtテ
ンティングまたは。Next, as shown in Fig. 2, the circuit pattern 5 formed in this way is placed on the copper foil 1, coated with 1~, and placed on the inside of the pattern along with the circuit board 6. After that, I used Gripreg 6 and connected it to the turret layer. In addition, I will drill holes and through holes. Next, the Daido pad section, the surface pattern t tenting with copper foil, and the surface pattern t with copper foil.
早出により株課し、大の周囲にノくラド等必会とされる
表口バクーンが残ゐようにして銅苗忙エツチング丁ゐ0
ベースとなった銅箔がエツチング除去されゐとあら27
1じめ形成さnた回路が基板内に埋め込まnk形で露出
て/)。By setting the stock early, the copper seedlings are busy etching, making sure to leave the necessary front openings such as Nokurad around the large ones.
The copper foil that served as the base has been etched away.
The first formed circuit is embedded in the substrate and exposed in the form of a circuit.
第6図は、このようにして侍らnた印刷配線板υ〜「l
凶を不すもので、7にスルホールめっき、8は内層回路
、4はめら〃・しめ形Jllll、ちれた回路で蕗出聞
には銅のエツチング液に耐蝕性のある金縞がめっきさt
してお91はエツチングざnずに残った銅箔であ/80
実施例
ステンレス(SUS4.5O−BA)表面にスコッチプ
ライト7448で研磨後、全回に50μm厚の憾敵銅め
つきt行なった0次に、フォトレジスト(リストンT−
121s)’cロール2ばネータによシノミネートした
0ポジマスク′9c尚て紫外勝′9c照射した佼、机保
歇tスプレーし現1数した0次に、金めつ@に1μmの
厚さで行ない、さらt/c供rR鋼めっきに30μm竹
なつた。レジスト剥離液に次潰し、レジストに剥離した
後、黒色酸化銅処理電行lっ7’(俊、パターンの形成
さnrt、銅箔τステンレス板よジはがし叡った。この
銅箔χあらかじめエツチング法で作成した内り板と接宥
用グリグレグと位置決めビンにより位置決めできる多層
化金型にセットし、170℃2時同60kg/an’の
圧力で)Ju #I加圧した。このようにしてm層した
着板にNCドリルに工す人めけt行なった埃、無電解め
っきによりスルーホールめ−)き葡竹なった0次に、フ
ォトレジスト(リストン’1’−1215)忙ラミネー
トし、大の周囲にバッドを形成するように焼付、現像に
行なった。就いて、内蔵さ71.た金めっ@か露出する
まで表向の調髪エツチングして所望の多層印刷配緋板忙
製t’lた0以上説明したように2本発明の印刷配腕板
のN遺伝に於ては次の利照か達成ちれゐ。Figure 6 shows the printed wiring board υ~'l
7 is through-hole plated, 8 is the inner layer circuit, 4 is a square/shime type Jllll, and the broken circuit is plated with gold stripes that are corrosion resistant to copper etching solution. t
91 is the copper foil that remained without being etched./80 Example: After polishing the stainless steel (SUS4.5O-BA) surface with Scotchprite 7448, 50 μm thick copper plating was performed in all cases. Next, photoresist (Liston T-
121s) 'c Roll 2 0 positive mask '9c was irradiated with ultraviolet light '9c. A 30 μm bamboo strip was applied to the T/C RR steel plating. After applying a resist stripping solution and stripping the resist, the copper foil treated with black oxide was peeled off from the stainless steel plate. It was set in a multi-layered mold that could be positioned using an inner plate prepared by the method, a gripper leg, and a positioning bottle, and pressurized at 60 kg/an' at 170°C for 2 hours. In this way, the m-layered board was coated with dust that was removed by an NC drill, and through-holes were formed by electroless plating. I laminated it, printed it to form a pad around the area, and then developed it. 71. The desired multi-layer printed scarlet plate is then fabricated by etching the outer surface of the plate until the gold plate is exposed. Next Riteru or achievement.
(υ 表面にキズの無い銅w1曲上にパターン葡形成す
るので劇中、蘇1!!J陥がそnぞれ100μm以下の
微細パターンを容易に侍ゐことかてさゐ0
(2) あらかじめ微細パターンχ形成した恢、積層
丁/bので、積層前に検丘でき歩留りか同上する0
(5)正確に形成さ2′L7′Cレジスト像の曲にめっ
きにより導体髪形成し、さらにこの導体か衝脂に埋め込
まn完盆に保映丁;bので、サイドエッチがなく、l#
A巾精良精度めて篩い。(υ Since the pattern is formed on the copper w1 piece with no scratches on the surface, in the movie, it is possible to easily handle fine patterns of less than 100 μm each. (2) Since the laminated plate/b is formed with a fine pattern χ in advance, it can be inspected before lamination to reduce the yield or the same as above. This conductor is embedded in grease and has no side etch, so there is no side etch.
A-width, high precision sieve.
(4) 第4図9に示すように耐鮭性金1j45、銅
4よりaゐ埋込まfした導体りみよりなる回路又10に
示すようにエツチングされずに残っ7C銅箔1Q;9−
よシなる回路、東に11に示すようにそれらの双方の導
体よ#)厄ゐ回路が任意に形成出来るため、広い範v5
の物性に応じた印刷配線板忙容易に製造することが出来
ゐ。(4) As shown in FIG. 4, a circuit consisting of salmon-resistant gold 1j45 and a conductor embedded in copper 4, or as shown in 10, 7C copper foil 1Q; 9-
A good circuit, as shown in Figure 11, is a conductor for both of them.
It is possible to easily manufacture printed wiring boards according to the physical properties of the board.
第1〜4図は本発明の方法ン祝明丁々にめの断1111
1因でめゐ。
符号の胱明
1 物量
2 レジストパターン
3 耐蝕性金属
4銅
5ti21wlIハz−ン
6 ズリプレグ
7 スルーホールめっき
8 内層回路Figures 1 to 4 show the method of the present invention.
For one reason. Code clarity 1 Quantity 2 Resist pattern 3 Corrosion resistant metal 4 Copper 5ti21wlI zone 6 Zuri preg 7 Through hole plating 8 Inner layer circuit
Claims (1)
ング液に耐蝕性のある全域のめっき、廟のめっきに行い
回路パターンを形成し、めっきレジストン除去し、回路
パターン面にプリグレグ會厘lt′:18せ加熱加圧し
た佐、穴あけ穴内壁の組めっ@塗付い、少なくともバッ
ト部に含む必賛とされる銅箔による表面パターンに対応
するエツチングレジスト會形成後銅箔忙エツチング丁ゐ
こと′9C峙倣とする印桐配線板の製造法。1. Apply a plating resist between pieces of copper foil, apply a copper etching solution to the entire area with corrosion resistance, form a circuit pattern by plating the mausoleum, remove the plating resist, and apply a pregreg to the circuit pattern surface. 18 After heating and pressurizing, assembling the inner wall of the drilled hole and coating it, and etching the copper foil after forming an etching resist that corresponds to the surface pattern of the copper foil that is included at least in the butt part. A method for manufacturing an Indo paulownia wiring board based on the '9C pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10127083A JPS59227185A (en) | 1983-06-07 | 1983-06-07 | Method of producing printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10127083A JPS59227185A (en) | 1983-06-07 | 1983-06-07 | Method of producing printed circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59227185A true JPS59227185A (en) | 1984-12-20 |
JPS6337515B2 JPS6337515B2 (en) | 1988-07-26 |
Family
ID=14296190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10127083A Granted JPS59227185A (en) | 1983-06-07 | 1983-06-07 | Method of producing printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59227185A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005311202A (en) * | 2004-04-23 | 2005-11-04 | Matsushita Electric Works Ltd | Wiring board and manufacturing method thereof |
US7868464B2 (en) | 2004-09-16 | 2011-01-11 | Tdk Corporation | Multilayer substrate and manufacturing method thereof |
WO2011078031A1 (en) * | 2009-12-22 | 2011-06-30 | 株式会社メイコー | Process for production of printed circuit board, and printed circuit board |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03613A (en) * | 1989-05-17 | 1991-01-07 | Dainippon Printing Co Ltd | Electronic component carrying body composing device |
JPH0462605U (en) * | 1990-10-09 | 1992-05-28 |
-
1983
- 1983-06-07 JP JP10127083A patent/JPS59227185A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005311202A (en) * | 2004-04-23 | 2005-11-04 | Matsushita Electric Works Ltd | Wiring board and manufacturing method thereof |
JP4534575B2 (en) * | 2004-04-23 | 2010-09-01 | パナソニック電工株式会社 | Wiring board manufacturing method |
US7868464B2 (en) | 2004-09-16 | 2011-01-11 | Tdk Corporation | Multilayer substrate and manufacturing method thereof |
WO2011078031A1 (en) * | 2009-12-22 | 2011-06-30 | 株式会社メイコー | Process for production of printed circuit board, and printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
JPS6337515B2 (en) | 1988-07-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6548153B2 (en) | Composite material used in making printed wiring boards | |
JPH06318783A (en) | Manufacturing method of multilayered circuit substrate | |
JPS59227185A (en) | Method of producing printed circuit board | |
CN115802601B (en) | Flush printed circuit board and production method thereof | |
JP3650514B2 (en) | Method for manufacturing printed circuit board with plated resistor | |
JPH01290289A (en) | Method of forming conductor pattern | |
JPS6182497A (en) | Manufacture of printed circuit board | |
JP2000036662A (en) | Manufacture of build-up multilayer interconnection board | |
JPH10321970A (en) | Printed wiring board and manufacture thereof | |
JP3599957B2 (en) | Method for manufacturing multilayer wiring board | |
JP3288290B2 (en) | Multilayer printed wiring board | |
JPH0690087A (en) | Manufacture of multilayer printed wiring board | |
JPH04127494A (en) | Multilayer printed wiring board | |
JP2000151073A (en) | Manufacturing wiring board | |
JPH03225894A (en) | Manufacture of printed wiring board | |
JP2768122B2 (en) | Method for manufacturing multilayer wiring board | |
CA1234923A (en) | Method for manufacturing multi-layered printed circuit boards and a circuit board produced by same | |
JPS59175797A (en) | Method of producing multilayer printed plate | |
JPS63202086A (en) | Manufacture of printed circuit board | |
JPS5832798B2 (en) | Manufacturing method for printed wiring boards | |
JP2768123B2 (en) | Method for manufacturing multilayer wiring board | |
JPH0158878B2 (en) | ||
JPS62277789A (en) | Manufacture of wiring board | |
JPH08279682A (en) | Manufacture of multilayered circuit board | |
JPH0366831B2 (en) |